2021 Conference Program

9:00 a.m. – 5:00 p.m.
1: PCB Design for Engineers – Part One (Two Day Course)
Speaker: Susy Webb, CID, Design Science

This class will feature an overview of the entire process of board design, from start to finish, addressing the EE designing their own boards or the new designer who needs to thoroughly understand all the steps and processes. We start with a conversation of the electronics and physics involved and discuss why rise time and controlling the energy fields are extremely important to the signals on the board. Choosing part types that are effective (outside of their electronics) will be next, so we can discuss what works well for signal flow and mounting possibilities. Then we look at the schematic and possible signal and constraint issues. As we dive into the board mechanicals, we will discuss determining routing layer count, planes for return current, and stackup control for impedance control. Placement comes next, with considerations for the electronics and setting up routing. Many facets of fanout and routing will be explored, including HDI vias for dense boards, spacing considerations, and layer paired routing for low noise, followed by a discussion of the capacitance and power distribution. Many aspects of making a board manufacturable will wrap things up, followed by information on the pros and cons of hand routing vs. autorouting

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Intermediate
9:00 a.m. – 4:30 p.m.
2: Power Delivery System Design
Speaker: Lee Rtichey, Speeding Edge

With the advent of ICs with multiple power rails at very high currents, the design of the power delivery system in a modern product is often more difficult than routing the PCB to ensure good signal integrity. The power delivery system must deliver power to devices at frequencies from D to hundreds of megahertz. The applications notes that accompany most ICs do not contain adequate information to allow a designer to correctly design the PDS.

This all-day course is aimed at providing the information needed to get the job done right. It draws on the speaker’s experience designing hundreds of power delivery systems for products ranging from satellites to super computers. It contains a very large number of test PCBs used to determine how well each component will perform when used in a PDS.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. – 12:30 p.m.
3: IoT/Low Layer Count PC Board Design
Speaker: Rick Hartley. RHartley Enterprises

Circuit boards for the IoT (Internet of Things) world are often driven by the need for low power dissipation, low cost (which drives very-low-layer count), moderate- to high-density and mixed-signal applications. This combination of needs can make the board design an extreme challenge. Creating a 1-, 2- or 4-layer board with excellent signal integrity and low noise/interference and no EMI issues can, by itself, be a serious challenge.

This 3.5-hour course will discuss when it is necessary to control impedance of lines, how to do it cost-effectively, proper setup of routed lines to keep circuit energy from spreading (preventing interference), even on a one-layer board, design of antenna into the PCB, circuit grounding in low-layer-count boards, power distribution without the benefit of power planes, ground bounce, and crosstalk with low-layer-count PCBs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. – 4:30 p.m.
4: PC Board Design for Optimum Fabrication and Assembly
Speaker: Rick Hartley, RHartely Enterprises

Many engineers believe the cost of bare boards and assemblies is purely a function of board size, thickness, number of layers, spacing between features, etc. Part of that statement is true, but certainly not all of it. Many things drive cost of both.
More important, many PCB design issues determine the quality of both bare boards and assemblies, such as where copper is located and its density, part placement, how the board is routed, balanced PCB stack-up, feature sizes, etc.

This 3.5-hour session will focus on how to accomplish the goal of both low cost and high quality with just a few simple concepts. Bottom line: When boards are not designed properly, fabricators and assemblers must make modifications to the design to produce them. Sometimes their modifications cause the boards to malfunction. If we design correctly, this will not happen.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate
3:30 p.m. – 4:30 p.m.
5: PCB Design Optimization: What it Means and New Methods
Speaker: Zachariah Peterson, Northwest Engineering Solutions

PCB designers often speak of “design optimization,” and causal PCB design optimization has found a stronger mathematical footing in the engineering literature over the last 10 years. In particular, transmission line design requires satisfying multiple design objectives and constraints that may be in conflict, and engineers need tools and methods to help them balance design objectives while staying within their design constraints. For ultra-high-speed boards, designers need to optimize transmission line designs within the relevant signal bandwidth, which can extend to hundreds of GHz. Newer signaling specifications and standards (e.g., USB4, DDR5, and IEEE 802.3 standards) require this level of optimization throughout the signal bandwidth to demonstrate compliance, and design teams need a set of tools that help expedite this type of optimization. Current PCB design optimization methods are typically measurement-based or field-solver-based, but CAD packages lack support for these tasks or for accepted analytical methods in PCB design optimization.

This presentation outlines the current state of PCB design optimization techniques used to produce useful designs, while balancing multiple design goals. An alternative method for design optimization from analytical equations describing transmission lines will be presented. Some practical examples for striplines, microstrips, and mode-selective waveguides will be presented. These models are fully causal and account for dispersion, dielectric losses, skin effect losses, and copper roughness in a real PCB. The presented method is applicable to any transmission line with a known analytical or numerical model, and the method uses standard evolutionary computation techniques to optimize the design. Similar techniques can be implemented in advanced field-solver tools, but designers with basic coding skills can use some simple open-source packages to build their own design optimization routines for transmission lines. Furthermore, the transmission line design optimization method presented here can be used to balance multiple design objectives, which is not currently possible in PCB CAD packages.

Who should attend: PCB Designer/Design Engineer, System Designer, SI Engineer
Target audience: Intermediate, Advanced
9:00 a.m. – 5:00 p.m.
6: PCB Design for Engineers – Part Two (Two Day Course)
Speaker: Susy Webb, CID, Design Science

This class will feature an overview of the entire process of board design, from start to finish, addressing the EE designing their own boards or the new designer who needs to thoroughly understand all the steps and processes. We start with a conversation of the electronics and physics involved and discuss why rise time and controlling the energy fields are extremely important to the signals on the board. Choosing part types that are effective (outside of their electronics) will be next, so we can discuss what works well for signal flow and mounting possibilities. Then we look at the schematic and possible signal and constraint issues. As we dive into the board mechanicals, we will discuss determining routing layer count, planes for return current, and stackup control for impedance control. Placement comes next, with considerations for the electronics and setting up routing. Many facets of fanout and routing will be explored, including HDI vias for dense boards, spacing considerations, and layer paired routing for low noise, followed by a discussion of the capacitance and power distribution. Many aspects of making a board manufacturable will wrap things up, followed by information on the pros and cons of hand routing vs. autorouting.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Intermediate
9:00 a.m. – 12:30 p.m.
7: RF and Mixed Signal PCB Layout
Speaker: Rick Hartely, RHartley Enterprises

This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.

Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PCBs, mixing RF with digital, or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. This course will cover differences between analog and digital, circuit changes over time, lumped vs. distributed length lines, reflections/return loss/VSWR, low- and high-frequency current, transmission line behavior, impedance control, microstrip vs. stripline, coplanar waveguide with ground, circuit termination, 1/4 wavelength couplers and filters designed into board copper, layout techniques and strategies, critical routing and circuit isolation, ground plane splitting (when to and when not to), mismatched loads and other discontinuities, signal splitters, tuning transmission lines, power bus decoupling for RF vs. digital circuits and board stackups for mixed RF and digital circuits.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate
9:00 a.m. – 11:00 a.m.
8: (FREE) The 21 Most Common Design Errors Caught by Fabrication (and How to Prevent Them)
Speaker: Ray Fugitt, DownStream Technologies, and David Hoover, TTM

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We started with 10, and based on popular demand, we’ve expanded and keep updating that list! We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will have knowledge to assist them in using their existing tools to produce better and more accurate designs. This year we have asked another FAE to join us with his insights to what he sees on incoming data as well.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
11:00 a.m. – 12:00 p.m.
9: Improving Circuit Design and Layout for Accessibility and Success
Speaker: Tomas Chester, Chester Electronic Design

With this seminar, attendees will be given details and examples of additional information that can be embedded within their existing design process. This content is aimed at improving the successful outcome of their design and reducing the time spent acquiring circuit, component, or layout knowledge. Whether you are a solo designer or an engineer within a large team, these design additions will enable participants to look beyond their own immediate workflow and improve the project design process.
The seminar will focus on project foresight, multi-channel/multi-project design reuse, and identical characterization during the entire development cycle.
The following topics will be covered: component/library creation for future/multi-project use, schematic accessibility and complexity reduction, printed circuit schematic and layout design strategies for verification and debug, and procedural interactions of a successful project.
Attendees will gain methods for improving design success: design examples and experience interacting with various project states, methods for reducing verification and debug cycles, and multi-user interactive perspectives.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner
2:00 p.m. – 3:30 p.m.
10: PCB Design Techniques to Improve ESD Robustness
Speaker: Daniel Beeker, NXP Semiconductor

Raise the shields, Scotty! Starting with some simple definitions for ESD/EOS, this session describes the important differences in the energy involved and the type of damage that can result. The presentation focuses on PCB design techniques as a means of improving system robustness.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate
3:00 p.m. – 5:00 p.m.
11: PCB Layout of Switch Mode Power Supplies
Speaker: Rick Hartley, RHartley Enterprises

When executing PCB layout, we tend to treat digital circuits differently from analog circuits. Each has its own critical requirements. Switch mode power supplies are another wrinkle altogether, and usually need to be treated differently from either. All switch mode power supplies have four to five circuit loops, all of which are important, but a couple of these loops are downright critical in terms of PCB layout. An improperly designed switch mode supply will often not function as intended, and in some cases will not function at all. In contrast, understanding what makes up a switcher circuit and knowing how to take care of the loops during board layout will permit these supplies to operate flawlessly with very-high efficiency.
This two-hour course will outline the difference between switchers and series regulated power supplies, the different types of switcher circuits (buck, boost, etc.), basic theory of operation of switcher circuits and the impact of the various components, definition and behavior of the five loops, layout to isolate loops from one another, minimize voltage drop, and control current paths, layout to minimize noise and EMI, effect of paralleling output capacitors and proper grounding technique.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
 
 
9:00 a.m. – 12:30 p.m.
14: 7 Innovative Solutions for Hybrid Boards
Speaker: Michael R. Creeden, CID+, Insulectro

The complexity of needs in today’s hybrid circuitry such as RF, HSD and antenna are becoming common to find all types on one board. Learn how innovations with hybrid materials help solve most hybrid circuit challenges.
Hybrid boards are not new to the industry, but many of the solutions are based on outdated constructs, and it’s time for some innovation. With this presentation, attendees will receive many examples of how to construct and solve a board with most concerns of today’s 5G performance challenges: dense high-speed digital, RF and antennas, and many more, addressing HDI solvability, signal integrity/EMI, PDN and improved manufacturability.

Attendees will receive an understanding of basic EM theory with a strong emphasis on material and process solutions that help routing application. This starts with data capture, rules definition, and tool automation, then covers routing perspectives from the start of the layout cycle, all the way to the review and verification stages, into generation of deliverables for manufacturing. Emphasis is on the role that EM fields play to manage the circuit to be cost-effective, perform well electrically and be a reliable high-yield product. We will touch on all types of circuit technologies in many market segments.

The focus is on integration between design and manufacturing early in the development cycle to build a product that is correct-by-construction and performs on Revision-1.

We will cover a wide range of topics, including hybrid material selection for rigid and rigid-flex; rationale for considering HDI; placement, routing techniques, power delivery, and EMI shielding; and technological challenges from design through manufacturing process.
Students will learn what it takes to successfully implement these concerns: complex solvability; high-speed, RF and thermal performance; and high yield and reliable manufacturability.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator, Engineer/Operator
Target audience: Intermediate, Advanced

9:00 a.m. – 12:30 p.m.
15: Effective PCB Design: Techniques to Improve Performance
Speaker: Daniel Beeker, NXP Semiconductor

As IC geometries continue to shrink and switching speeds increase, designing electromagnetic systems and printed circuit boards to meet the required signal integrity and EMC specifications has become even more challenging. A new design methodology is required. Specifically, the utilization of an electromagnetic physics-based design methodology to control the field energy in your design will be discussed. This training module will walk through the development process and provide guidelines for building successful, cost-effective printed circuit boards.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Intermediate

9:00 a.m. – 3:30 p.m.
16: Printed Circuit Board Stackup Design for High Performance Product
Speaker: Lee Ritchey, Speeding Edge

This comprehensive seminar explains how to design a PCB stackup to optimize performance, while attaining the lowest cost possible. With the advent of very-high-speed signaling along with multiple very-high-current power supply rails, it is necessary to understand how materials behave and how PCBs are fabricated in order to arrive at a PCB stackup that results in a “right the first time” design.

The seminar draws from the speaker’s long experience designing PCB stackup for products ranging from video games to super computers. It draws on the results of dozens of test PCBs used to characterize materials from a loss and high-speed skew perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced

1:30 p.m. – 3:30 p.m.
17: From DC to AC – Power Integrity and Decoupling Primer for PCB Designers
Speaker: Ralf Bruening, Zuken

Today, supply voltages decrease with every new silicon generation, contributing as well to the goal of reducing power consumption of electronics. This and the resulting shrinking noise margins for these ICs define increasing demands for the quality and stability of power distribution systems of the PCBs. Shrinking form factors with decreasing board real estate (e.g., IoT devices) and emerging technologies (e.g., autonomous driving, advanced communication units) add fuel to the fire. Hence tighter requirements and constraints from silicon vendors are defined for the power distribution networks (PDN) PCB designers have to follow and implement in conjunction with tighter decoupling schemes. Application-dependent restrictions (e.g., discrete package allowance in automotive) and stringent cost and quality demands further complicate the game.

In this two-hour workshop, the requirements and the basics of PCB power distribution systems are explained in detail. Plate capacitance, loop inductances and cavity resonance are explained without deep math. Side effects to the signal integrity (SI) and EMC behavior of board structures are discussed using illustrated practical examples. The role of decoupling capacitors and their evolution in recent years are a major part of the workshop. Guidelines for a first order covering and resolving power integrity issues are given regardless of the used PCB-design and ECAD process. Simulation capabilities addressing power integrity (PI) during PCB design will be explained and demonstrated by animated slides in a generic, vendor-neutral manner as one powerful problem-solving approach for PI issues. Silicon vendor support documents (e.g., design guidelines, constraint-documents, reference designs or spreadsheet tools) to address power integrity are introduced and discussed. Examples from various industries (e.g., automotive) will complement the session with practical application experience.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate

1:30 p.m. – 3:30 p.m.
18: Electromagnetic Fields for Normal Folks: Show Me the Pictures and Hold the Equations, Please!
Speaker: Daniel Beeker, NXP Semiconductor

The material presented will be focused on the physics of electromagnetic energy basic principles, presented in easy-to-understand language with plenty of diagrams. Attendees will discover how understanding the behavior of EM fields can help design PCBs that will be more robust and have better EMC performance. This is not rocket science, but an easy-to-understand application of PCB geometry. It’s all about the space!

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner