2023 Conference Program

Register now!

10 a.m. to 12 p.m.
1: Differential Pair Design Masterclass
Zachariah Peterson Northwest Engineering Solutions LLC

Differential pairs are the primary routing style used in many high-speed digital protocols. The guidelines surrounding differential pair design and routing are very important for signal integrity, yet designers may be prone to implement the default rules from their CAD tools when designing and routing differential pairs. In this presentation, we will address some of the longstanding myths surrounding differential pairs:

  • What factors affect differential pair impedance
  • The difference between odd-mode and characteristic impedance
  • The ambiguity and fallacy of tight coupling
  • Noise and crosstalk involving differential pairs
  • Why it’s sometimes best to limit length tuning
  • SI factors such as mode conversion and reflections
  • How to correctly route through vias in differential pairs.

Examples of real systems that were designed by the author and have entered volume manufacturing will be presented to illustrate these important concepts. Simulation examples will also be used to help illustrate the importance of certain design choices, and to illustrate some basic rules of thumb that help ensure signal integrity.

Who should attend: PCB Designer/Design Engineer, SI Engineer
Target audience: Intermediate, Advanced
10:00 a.m. to 6:30 p.m.
2: PCB Design for Engineers
Susy Webb Design Science

This class will feature an overview of the processes of board design from an engineering perspective. To begin, we will have a conversation about how the electronics and physics are involved and why controlling rise time, field energy, and transmission lines are extremely important to the signals on the board. Placement will be discussed next, with order, flow, and setting up potential routing to come being some of those topics.

The planes and stackup structure will play a major role in the quality of the design and impedance control, especially if the design is high-speed, and plane and capacitor placement are a large part of power distribution as well. The way signals are routed and how their return current is set up is critical for their performance. We will discuss fanouts, using grids, the signal flow from layer to layer, layer-paired routing and spacing.

HDI technology can be a huge benefit to dense boards, fine-pitch parts, and BGAs, and we will review their setup and routing. All these topics will include information on signal integrity, EMI and impedance control, to make a board that works well from the first build.

Many aspects of making a board manufacturable also help to make it less expensive, so an examination of that will wrap up the technical information, followed by information on pros and cons of hand-routing vs. autorouting and the board quality.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
10:00 a.m. to 6:30 p.m.
3: PCB 102: How PCB Design Requirements Affect Fabrication
Paul Cooke Ventec

This course will walk the audience through the entire multilayer PCB fabrication process, making stops along the way to explain how PCB design requirements affect the numerous fabrication steps and if/how the finished product can meet the intended quality and reliability requirements. A detailed explanation will be given for each of the process steps and how that step affects quality and reliability.

Design requirements will be discussed, with an explanation of the do’s and don’ts of how they affect fabrication and impact yields.

Process controls adopted by the fabricator to ensure maximum yields and quality are maintained during each step of fabrication will also be covered, as well as the pros and cons of variables available to the designer: solder mask, surface finish, materials selection, copper weights, feature size, etc.

The course also looks at fabrication drawing specifications and how they can affect yield, cost, quality and reliability.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Intermediate, Advanced
1:30 p.m. to 2:30 p.m.
4: How to Modularize Your IoT Design and Build Systems for the Future
Ethan Pierce Pierce Design

Technical teams are driven to design modular IoT devices and future-proof systems:

  • To keep pace with new technologies coming to the market.
  • To add additional functionality to existing systems they may or may not have control of
  • Reduce system cost and SKU fragmentation.

The purpose of this course is to equip designers and engineers with the knowledge to consistently design modular systems that stay ahead of the technology curve. Technology moves at an exponential rate and is a consistent challenge for designers, and engineers attempting to maintain pace in their designs for new and existing systems. Using industry trends around past, present, and future hardware designs this course attempts to identify a framework and pattern to allow designers to make systems more modular and adaptable. Once equipped with this knowledge, participants can approach systems with the ability to introduce additional technology and features with the added modularity. This course presents a pattern of thinking to maintain the pace of technology and participants can then apply this to their designs.

This course is for:

  • Junior and mid-level electrical engineers
  • Junior and mid-level PCB designers

Included in the course we will introduce:

  • High-level framework for thinking about and designing with modular hardware systems
  • Electrical and mechanical considerations in system architecture for modularity
  • Interposing boards between modulars systems
  • When to modularize vs. integrate
  • Impact on manufacturing and operations teams.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate
2:30 p.m. to 6:00 p.m.
5: Circuit Grounding to Control Noise and EMI
Rick Hartley RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent.

This 3.5-hour course will focus on the issues PCB designers and engineers need to know to prevent noise, EMI and grounding problems in today’s circuits. We will discuss what is meant by “grounding,” where energy travels in the board, location of high- and low-frequency currents, keys to controlling common mode EMI, cables and other unintended radiators, effects of IC style and packaging on overall grounding, impact of connector pin-out, best locations for IO connectors, divided planes and plane islands in the PCB, routing to control noise, best board stack-ups and filtering of single-ended and differential I/O lines.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 11:00 a.m.
6: Making Intelligent Material Decisions
Michael R. Creeden, CID+ Insulectro

The complexity of needs in today’s hybrid circuitry such as RF, HSD and antenna is becoming common to find all types on one board. Learn how innovations with hybrid materials help solve most hybrid circuit challenges.

Hybrid boards are not new to the industry, but many of the solutions are based on outdated constructs, and it’s time for innovation. With this presentation, attendees will receive many examples of how to construct and solve a board with most of the concerns of today’s 5G performance challenges: dense high-speed digital, RF and antennas, and many more, addressing HDI solvability, signal integrity/EMI, PDN and improved manufacturability.

Attendees will receive an understanding of basic EM theory with a strong emphasis on material and process solutions that help routing application. This starts with data capture, rules definition, and tool automation, and covers routing perspectives from the start of the layout cycle, all the way to the review and verification stages, into generation of deliverables for manufacturing. Emphasis is on the role EM fields play to manage your circuit to be cost-effective, perform well electrically and be a reliable high-yield product. We will touch on all types of circuit technologies in many market segments.

Focus is on integration between design and manufacturing early in the development cycle, to build a product that is correct-by-construction and performs on Revision-1.

We will cover a wide range of topics, including:

  • Hybrid material selection for rigid, rigid-flex and flex
  • Rationale for considering HDI
  • Placement, routing techniques, power delivery, EMI shielding
  • Technological challenges from design through manufacturing process.

Students will learn what it takes to successfully implement these concerns:

  • Complex solvability
  • High-speed, RF and thermal performance
  • High yield and reliable manufacturability.
Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Intermediate, Advanced
9:00 a.m. to 5:00 p.m.
7: Power Delivery System (PDS) Design
Lee Ritchey Speeding Edge

Today’s high-speed designs use a variety of power delivery components, and successfully designing a PDS and the PCB into which it is incorporated requires a thorough understanding of the overall power delivery system. In addition to reviewing the PDS components currently available, this course examines how to meet the conflicting goals of the PDS system and how to address power plane impedance and overall system capacitance issues.

This PDS design class is structured to take the student through the entire PDS design process. The class begins with the goals of the PDS design process, including how to arrive at a reliable design in the shortest amount of time and at the lowest cost possible with a minimal use of single-source suppliers and specialty components and materials.

The course will also examine several real-world PDS designs to further illustrate the goals of the design process.

The materials and examples used in this course are drawn from actual designs of PDS systems in current manufacture. These examples range from subminiature disc drives to terabit routers and supercomputers. The design process presented is based on many years of completing designs that are “right the first time.” The goal of the course is for students to take the information learned in class and start applying it immediately to troubleshoot existing designs or incorporate into next-generation product iterations.

Note: This is a 5.5-hour class. There is a break at the two-hour mark.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator
Target audience: Intermediate, Advanced
11:00 a.m. to 12:00 p.m.
8: HDI Via Design: Planning the Energy Pipelines
Daniel Beeker NXP Semiconductor

This session will focus on the challenges posed by using HDI vias from the perspective of layer transitions and power delivery. The example will use a 12-layer PCB to discuss the requirements for signal layer transitions. Via stackups will be defined to enable good signal integrity. Power delivery and the via structures necessary will also be addressed. A must-see class for anyone planning to use this technology.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Fabricator Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
9: The Complexities of Fine-Pitch BGA Design
Susy Webb Design Science

Designing with BGAs is much more challenging than in the past! The ball pitches are going down and the total pin counts and package size are going up, making everything more complex. With those changes, the signal integrity and EMI issues become more profound, the fanout and routing are much more challenging, and the power connections and thermal issues are more difficult. Add to that the manufacturing concerns that have surfaced from small pad openings and tiny capacitors, and the designer faces some real complex issues.

In this presentation, we will discuss all those things and more, including choosing effective BGAs, placement for components and caps, grid systems for parts and routing, some fanout possibilities, and some manufacturing issues unique to these kinds of designs with lots of illustrations and examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 11:00 a.m.
F1: PCB Design Techniques to Improve ESD Robustness
Daniel Beeker NXP Semiconductor

We all are involved with developing products which generate, control, and consume electromagnetic field energy. This is not what we are taught. Circuit theory suggests that electrical energy is made up of electrons moving in the conductors. Switches add conductors, and the current instantly starts to move in the loop. The wires carry the energy, and the load instantly responds to the flow of energy. Wrong! Switches add new spaces, and the moving field carries the energy. It takes time for the field energy to move into that space. The moving field energy has no idea what it is at the end of the new space. Field energy moving through a space is the current flow. The magic here is the displacement current flowing through the dielectric at the wave front, completing the circuit. Fields do all the work.

“Current flow” is a measure of moving field energy through a space. “Current flow” occurs in the space between the conductors that bound the dielectric. Some of the fields interact with the molecules in the outer surfaces of the conductors. This interaction consumes some of the field energy, hence a resulting voltage drop caused by this “resistance.”

The consumption of field energy results in increased movement of the molecules, hence is converted to “heat!” The dielectric also consumes energy the same way, unless it is a vacuum. Electromagnetic energy moves slower through a physical dielectric than through space. Field energy can only travel in space, not through matter. It takes time for the energy to go around the molecules it encounters. The higher the molecular density, the longer the path, hence, it takes the field longer to go from one place to another. Once created, EM field energy can only move from one space into another one as we intend, be converted into kinetic energy, or radiated into the surrounding spaces.

This course will, after an introduction to EM field behavior, and the concept of ESD and EOS, describe several effective methods for designing the spaces which will increase the overall robustness and immunity of a PCB. These methods also will result in a product which will have improved reliability as well.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Intermediate
11:00 a.m. to 12:00 p.m.
F2: Panel: What ECAD Designers are Having Problems With
 

 

Who should attend:
Target audience:
1:30 to 2:30 p.m.
F3: PCB Cost Drivers
Ryan Miller NCAB PCB

There are many key parameters of a PCB that determine cost. The needs of specification requirements drive the manufacturing process. In turn, each added manufacturing process affects PCB price and sustainability.

This presentation provides insight of how PCBs are priced for manufacturing according to the fabrication drawing and Gerber data. Hard cost drivers such as size, material and build complexity cannot always be changed, while they could have a significant impact on cost.

Soft cost drivers such as overspecification, lead times and transportation also may greatly affect price. An understanding of cost drivers helps engineers plan a more sustainable PCB and reduce costs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
2:30 to 3:30 p.m.
F4: Controlling the Waves: A Field-based Perspective on High-speed PCB Design
Daniel Beeker NXP Semiconductor

Good signal integrity and EMC start with a good PCB design philosophy. It is critical for design engineers to understand the behavior of EM fields. Proper design of the spaces these fields follow through the board is critical. Creating transmission lines that will meet the needs of the PDN and the fast-switching ICs in today’s high-performance products can be a challenge. Certain questions need to be answered to define the PCB geometry that will lead to a successful design. This seminar will present an easy-to-understand science-based approach for PCB design.

Attendees will leave this seminar with a better understanding of:

  • The basic behavior of EM fields as they move through the PCB and ways to control them
  • The most important characteristics of the ICs in the design that affect the PCB layout requirements
  • How to create an effective board stackup
  • How to use these characteristics to define the PDN component selection and placement, as well as the interconnects needed to create the transmission lines that support these requirements
  • How to use these characteristics to define the transmission lines that carry the high-speed signals.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
4:00 p.m. to 5:00 p.m.
F5: The Most Common Design Errors Caught by Fabrication (and How to Prevent Them)
Ray Fugitt, DownStream Technologies, and David Hoover, TTM Technologies

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We started with 10, and based on popular demand, we’ve expanded and keep updating that list!

We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We encourage attendee participation and ask folks to bring their challenges for discussion.

After this seminar, the PCB designer will have knowledge to assist them in using their existing tools to produce better and more accurate designs.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
10: Proper PC Board Layout of DDR2, 3, 4 & 5
Rick Hartley RHartley Enterprises

The majority of today’s digital systems utilize double data rate (DDR) memory. The advantages are many, mostly that we get twice the amount of information transfer per given “clock frequency.” More data transfer without increased signal integrity or EMI risk: fabulous!

Over the years, guidelines and rules have been developed, attempting to ensure DDR bus structures function as intended. Unfortunately, many rules are overly conservative and require excessive restrictions in PCB layout, adding time and cost to PCB design. Worse, these restrictions can add layers and cost to the PCB itself.

This presentation will focus on identifying reasonable rules and guidelines, as well as proper PCB layout concepts to ensure DDR structures function as intended without adding extra time or cost to the project.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
11: Place and Route for Dense High-Speed and RF Circuits
Michael Creeden Insulectro

With this presentation, attendees will receive a solid overview of place and route for dense high-speed and RF circuits. We will cover a wide range of topics including next generation materials, the rational for considering HDI for our products and overall layout flow.
We will discuss the technological challenges we face in both the schematic circuit rules capture, design layout and manufacturing process.

Students will learn what it takes to satisfy solvability, high-speed concerns, and RF performance issues, while still building a board that will be cost effective as a reliable, high-yield product. We will also review how our early integration with the manufacturing team during the design cycle will help us understand the specifics to build a product that is correct-by-construction and performs on Revision-1.

The class format follows the basic design flow as it typically exists. The class allows audience participation and involvement. The focus is on practical application and implementation using real world examples.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
12: Heat Management Strategies through Better Layout
Syed Ubaid Ali Wavetroniks

With continuous technology developments, electronic circuits are not only getting faster and smaller, but also more power hungry. As a consequence, related thermal issues are more prevalent than ever, because most PCBs these days comprise a number of high-power components such as high-performance processors, transceivers, MOSFETs, high power LEDs, etc., causing excessive heat.

Furthermore, power conversion circuitry such as DC-DC converters and regulators are major culprits behind temperature rise and hotspots. Besides the components, resistance of the electrical connections, copper traces and vias contribute to heat and power losses.

Thermal stress is one of the main causes of circuit malfunctioning, as it leads to a degradation of performance or even a possible malfunction or failure of the system. To combat thermal stresses at layout level, PCB designers need to incorporate effective techniques to reduce the impact of heating, such as careful selection of material, component selection, placement, power ground plane construction, thermal vias and a lot more.

We’ll learn all these effective strategies and tricks that a layout engineer can adopt to identify and mitigate major hotspots to improve thermal performance of PCBs.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Beginner, Intermediate
1:30 p.m. to 3:30 p.m.
13: Ask the Flexperts with Lessons Learned
Mark Finstad, Flexible Circuit Technologies, and Nick Koop, TTM Technologies

This course will cover the entire gamut of flexible and rigid-flex circuits from two of the most recognized names in the flexible circuit industry: Mark Finstad (co-chair of IPC-2223) and Nick Koop (co-chair of IPC-6013).

Topics covered will include mechanical design/material selection, cost drivers, bending and forming concerns, testing, and issues unique to rigid-flex.

This course also includes a complete virtual plant tour of a flexible circuit manufacturing facility to help attendees understand the manufacturing processes. Throughout the presentation, the instructors will share real-life stories of flexible circuit applications gained over 35+ years in the industry. Some are success stories, others not so much, but all provide excellent lessons learned.

The instructors also welcome and encourage questions and enjoy wandering off-course with lively interactive discussions on specific topics from the class.

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
14: Signals Flowing through a PCB
Susy Webb Design Science

When designing a PCB, the way the signals flow is critical to proper circuit function. Routing cannot be performed as a random connecting-the-dots methodology, but must be carefully thought out as to what layer the signals are on, where they go when they change layers, and how the return energy will get back to the source.

The first thing this presentation discusses is the physics of how the signal and its return energy flows within the structure of a board, and the planning that is needed. Then, we discuss how to control that energy to avoid interference by the way the signals and busses are placed. That will include discussing the damage that can be caused to signals by poor routing of noisy signals, poor placement and routing of buses, poor spacing between signals, or poor routing such as crossing splits in return planes.

Finally, we will discuss some stackup ideas for best containment and control of the energy.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. to 5:00 p.m.
15: RF and Mixed Signal PCB Design
Rick Hartley RHartley Enterprises

This session is intended for board designers to understand the things RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.

Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high-frequency analog PCBs, mixing RF with digital, or mixing low-frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board.

This course will cover

  • Differences between analog and digital
  • Circuit changes over time
  • Lumped versus distributed length lines
  • Reflections/return loss/VSWR
  • Low- and high-frequency current
  • Transmission line behavior
  • Impedance control
  • Microstrip vs. stripline
  • Coplanar waveguide with ground
  • Circuit termination
  • 1/4 wavelength couplers and filters designed into board copper
  • Layout techniques and strategies
  • Critical routing and circuit isolation, ground plane splitting (when to and when not to)
  • Mismatched loads and other discontinuities
  • Signal splitters, tuning transmission lines
  • Power bus decoupling for RF versus digital circuits
  • Board stackups for mixed RF and digital circuits.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate
3:30 p.m. to 5:30 p.m.
16: PCB DfM (A Comedy Routine Depicting a Typical Dialogue between a PCB Designer and Fabricator)
Stephen Chavez, Siemens, and Gerry Partida Summit Interconnect

PCB designers just don’t simply connect the dots or push the magic button, as some may suggest. They design complex PCBs that contain physical packages smaller than ever before while addressing electrical, mechanical, and thermal variables and cost. Success in PCB design means knowing and understanding what you are doing and how the decisions you make and implement upstream have downstream ramifications.

There are key factors in achieving success in PCB design. In this presentation, the speakers focus on the relationship between design and fabrication. We’ll discuss industry best practices within the design to fabrication process, along with the pros and cons that affect ROI when best practice recipes are implemented and when they are not implemented (the cost of doing nothing).

With today’s EDA tools, and eagerness of suppliers offering their technical support, the potential for success is higher than ever. This collaborative approach makes a positive difference in getting it right the first time, reducing respins (cost), increasing yields, and ultimately getting to market faster.

What you will learn:

  • Increase productivity and proficiency in PCB design to fab
  • Capitalize on existing industry best practices of DfM and manufacturing outputs
  • How you can reduce cost
  • A short comedy scenario depicting the dialogue between a principal PCB designer and a fabricator
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 p.m.
17: Avoiding PCB Respins, Reducing Cost and Time to Market
Syed Ubaid Ali, Wavetroniks

How often does it happen that we receive a schematic from the electrical engineer and the PCB layout starts in haste? Weeks of effort are spent and the layout completed based on our own understanding, but during the final review we realize the design doesn’t comply with the fundamental requirements, as they were never properly conveyed and documented. What now? It’s time for frustration and probably a design respin. This scenario can become worse if the issues are raised after fabrication and assembly.

Ever-increasing rising and falling clock edges of an IC demand an innovative and smart design approach rather than a conventional approach. In this session, we’ll discuss the best practices/standard operating procedure to overcome this situation effectively and efficiently.

What you will learn:

1. The collaborative approach to involve the major stakeholders early in the design phase.
2. What kind of documents and meetings are needed before kicking off the PCB layout.
3. How to acquire and document the mechanical requirements.
4. How to ask the EE to make the system block diagram effective and meaningful for the PCB designer.
5. How to understand the electrical side of the design and incorporate those insights into the layout.”

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
1:00 p.m. to 3:00 p.m.
18: The Mechanical Side of PCBs
Tomas Chester, Chester Electronic Design

All PCB projects have mechanical and physical parameters, from their size to how they are supported within their utilization, which have downstream impacts within our digital thread.

This seminar will take an in-depth look at a variety of existing EDA design tools and new mechanical methods that can be harnessed to yield a successful final product, while also examining the impact of stresses on the layer stackup.

Whether you are a solo designer or an engineer within a large team, the material covered will enable participants to identify and solve complex design problems.

This seminar will focus on:

  • Existing implemented mechanical PCB features
  • Advanced PCB fabrication techniques
  • Thermal solutions in the mechanical domain.

The following topics will be covered:

  • PCB mounting holes and backdrilling
  • Cross-sectional strength of stackups
  • Thermal transfer within PCBs and impact of heatsinks
  • Semi-flex and multi-stackup stepped PCB construction.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
3:00 p.m. to 5:00 p.m.
19: Principles of Building a PCB Stackup
Susy Webb, Design Science

The stackup of a printed circuit board is one of the most important parts of the design layout. It affects the way the signals flow on the board, so it can affect many other aspects of the functioning board, like impedance control, return current and the amount of crosstalk, common mode currents, and displacement currents. In today’s higher-speed designs, it is critical to do this step well.

We will discuss what is needed for a good stackup, and the routing thereon, both from an electronic and a manufacturing perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced