2024 Conference Program

Register by May 3rd, 2024 and Save $200!

Register now!

9:00 a.m. to 10:00 a.m.
1: PCEA Annual Meeting
Stephen Chavez, Siemens

Come learn about the Printed Circuit Engineering Association, an international network of engineers, designers, and anyone related to printed circuit development. Its mission is to promote printed circuit engineering as a profession and to encourage, facilitate, and promote the exchange of information and the integration of new design concepts through communications, seminars, workshops, and professional certification through a network of local and regional PCEA-affiliated groups.

Who should attend: PCB Designer/Design Engineer, System Designer, Fabricator Engineer/Operator, Assembly Engineer/Operator, Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 6:00 p.m.
2: PCB Design for Engineers
Susy Webb, Design Science

Many engineers are now required to design their own PCBs, but have not had the benefit of learning the particular needs of the electronics, signals, placement, routing and manufacturability in those boards.
This class will feature an overview of the processes of board design from an engineering perspective. To begin, we will have a conversation about the electronics and physics involved and why controlling rise time, field energy, and transmission lines is extremely important to the signals on the board. Placement will be discussed next, with some of those topics including order, flow and setting up potential routing to come. The planes and stackup structure will play a major role in the quality of the design and impedance control, especially if the design is high-speed; and plane and capacitor placement are a large part of power distribution as well. The way signals are routed and how their return current is set up is critical to performance.

Also discussed:

  • Fanouts
  • Grids
  • Signal flow from layer to layer
  • Layer paired routing and spacing.
  • HDI technology can be a huge benefit to dense boards, fine-pitch parts and BGAs, so we will go over their setup and routing.

All these topics will include information on signal integrity, EMI and impedance control, to make a board that works well from the first build. Many aspects of making a board manufacturable also help to make it less expensive, so an examination of that will wrap the technical things up, followed by information on the pros and cons of hand routing vs. autorouting and impact on board quality.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 12:00 noon
3: DDR5 Through the Eyes of the Designer
Charlene McCauley and Terrie Duffy, McCauley Design Group

How to reach the maximum capacity interactions between processor and memory using the new Dell/Jedec CAMM connector. The demand for speed is here and now from media, CAD, 3-D design, scientific research and data analysis, AI, and machine learning. This presentation aims to explore through the eyes of the designer the key design challenges when routing DDR5, from processor and memory placement considerations to maximum speed and performances.

  1. What is the CAMM connector on external modules, not mother board
  2. DDR5 vs. previous DDR
  3. LPDDR vs DDR
    1. Voltage differences
    2. DRAM layout difference
    3. Constraint differences
    4. Placement and pattern of DRAMs
    5. Pattern of DRAM placements
    6. To mirror or not
    7. Sharing command addresses
    8. Length matching philosophies. SODIMM vs CAMM
    9. Offsets for length matching
    10. Special cases of length matching
    11. Single channel/dual channel
    12. Signal impedance
    13. Planes.
Who should attend: Designer/Design Engineer, System Designer, Hardware Engineer
Target audience: Intermediate, Advanced
10:00 a.m. to 12:00 noon
4: Test Structures and Economical Nondestructive Measurement Techniques for Multilayer PCB Impedance Characterization
Tim Wang Lee, Ph.D., Keysight Technologies

In the ever-evolving landscape of printed circuit board (PCB) design, the role of simulation has become important in ensuring optimal performance and averting system failures. While simulation offers valuable insights, discrepancies between designed and fabricated PCBs can arise due to manufacturing process variations.

Bridging this gap between theory and reality requires a deeper understanding of the as-fabricated properties, enabling designers to enhance correlation and prevent unexpected failures.

This presentation delves into a comprehensive approach to improving the correlation between simulation and measurement for multilayer PCBs. The presenter introduces innovative test structures and nondestructive measurement methodologies that provide essential insights into PCB material properties and cross-sectional geometry, all while considering simulation aspects.

Key points to be covered:

  1. Manufacturing variations: Understand the impact of manufacturing process variations on PCB performance.
  2. Test structures and nondestructive methods: Explore novel test structures and economical measurement techniques.
  3. As-fabricated parameters: Extract key as-fabricated parameters, including trace width, substrate height, and bulk dielectric constant.
  4. Simulation-informed modeling: Demonstrate how extracted properties predict possible failures.
  5. Manufacturing process monitoring: Learn how these techniques serve as a robust monitoring mechanism for PCB manufacturing.
    What you will learn:

    1. Signal integrity insights: Gain a deeper understanding of the impact of cross-sectional geometry variations on PCB signal integrity.
    2. Practical application of EM theory: Revisit the interplay between electrical parameters and physical properties on a PCB.
    3. Economic measurement techniques: Discover test structures and nondestructive methods for extracting PCB cross-sectional parameters.

    By exploring the interplay between simulation, design, and manufacturing, this presentation equips PCB designers, hardware engineers, and SI scientists with invaluable tools and insights to create high-performance PCBs that meet the demands of today’s fast-evolving electronic landscape.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate
12:00 p.m. to 1:00 p.m
Lunch-N-Learn (Tuesday Conference Attendees Only)
Sponsored by Polar Instruments
1:30 p.m. to 3:30 p.m.
5: Five Pillars of Your PCB Library
John Watson, Palomar College

With ever-increasing challenges in the electronic industry, an exemplary component library is essential. Everything begins and ends in the PCB library. Furthermore, the quality of the design is directly related to the quality of the components and our library.

Although every library is different, I have found five common principles that must be in every one of them to be a success. Using the acronym S.M.A.R.T., we will examine it in detail.
First Pillar: Singularity. No matter the size of the design team, if they are working from different data as their starting point, it doesn’t take a psychic to determine the results of that one. There is no way to control the results. It is like multiple people starting at different locations, going in different directions, each having another map, and expecting them to end up at the same place. The dangers and results of using rogue libraries are significant. We look in detail at the importance of this first principle of our library. How to have and maintain a Single Source of Truth.

Second Pillar: Managed. Managing the component data and models is the principle we take up with this pillar. The principles and methods of managing data, including revisioning, lifecycle scheme, roles and permissions: the importance of identifying the warning signs that you are no longer in control. Our objective here is to implement a plan to maintain the integrity of the library.

Third Pillar: Architecture. With massive amounts of data, how the library is organized determines how easy it is to find precisely what you are looking for. This brings up the issue of naming conventions for your components. Organizing the number of components now on the market in the billions can be daunting. Luckily, it turns out that everyone has the same structure in the sense they all have a category, a family, and sometimes a subfamily.

Fourth Pillar: Reviewable. What steps are required to review the components in the library to ensure it is correct? Which sources would be referred to to provide as much data as possible to ensure the correct component? Two standards should exist in every company: the procedure to create a correct component and the quality control procedure.

Fifth Pillar: Traceability. As noted, everything begins and ends in the library. This is not a linear process but a circular one, where information and data are collected, and feedback into the library to determine if changes are needed.

This pillar could be better described as the ongoing data review to improve it with each design continually. What exactly is the goal of the traceability area? What specific reports should be considered to allow a self-explanatory picture of the ongoing quality of each component?
When changes occur on the components level, we must first manage that change.

Who should attend: PCB Designer/Design Engineer
Target audience: Beginner
1:30 p.m. to 5:30 p.m.
6: Circuit Grounding to Control Noise and EMI
Rick Hartley, RHartley Enterprises

When time-varying (AC) signals travel in the transmission lines of a board, state-changing electric and magnetic fields are present. These fields, when not controlled, are the source of noise and EMI. In recent years, ICs with very fast rise time outputs have made problems common, even in circuits clocked at low frequencies. Knowing all the basics of proper grounding will help contain and control fields, making noise and EMI issues virtually nonexistent.

This 3.5-hour course will discuss and define:

  • “Grounding” defined and energy movement in a PCB
  • Keys to controlling common mode Energy and resulting EMI
  • Cables, heat sinks, board edges and other unintended radiators
  • Effects of IC style and packaging on overall grounding scheme
  • Impact of connector pin out on containment of energy
  • Divided planes and plane islands in the PCB
  • Best PCB stack-ups for optimum grounding schemes.
Who should attend: “PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer “
Target audience: Beginner, Intermediate, Advanced
2:30 p.m. to 5:00 p.m.
7: Designing for Reliability: Design Choices have Cleanliness Consequences
Caleb Buck , EaglePicher

You’ve done it! You have created the perfect design that will meet all of your customer’s signal integrity requirements! However, you were not aware that your design choices have cleanliness consequences and now your customer informs you that your “perfect design” has failed in the field. Their investigation finds that this failure was caused by flux residues that grew dendrites, causing a short circuit. In this situation it is easy to point the finger at whomever assembled the PCBAs, but a number of design choices likely could improve the cleanability of a design.

In this presentation you will learn how to design for reliability by making proactive design choices that will greatly reduce the failure rate of a design in the field. You will learn about the various PCB cleanliness failure modes and how end-use environmental factors contribute to system reliability. We will also explore how to find cleanliness failures when things don’t go as planned.

The majority of this presentation will focus on specific design choices that can be made and how exactly those design choices help or hurt the cleanability of a design.

Topics covered:

  • Cleanliness verification methods
  • Flux selection
  • Component geometry
  • Layout for cleanliness techniques
  • Conformal coating
  • Cleaning methods.

SIR test results from my ongoing PCB cleanliness case study will be shared throughout the presentation as objective evidence for these design concepts.

What you will learn:

  • How cleanliness failures occur
  • How to avoid failures by being proactive in design choices
  • How to design for reliability.
Who should attend: PCB Designer/Design Engineer, Hardware Engineer, Test Engineer, Assembly Engineer/Operator
Target audience: Beginner
9:00 a.m. to 10:00 a.m.
8: “Copper Pours” on PCB Signal Layers
Rick Hartley, RHartley Enterprises

“Debate is ongoing among many printed circuit design engineers about the use of copper pour segments in or on some layers of PCB. Some say copper pours can increase crosstalk, change impedance of transmission lines, increase EMI, or have an impact on power delivery, etc. Others say that the opposite is true. This session will discuss the “real” impact, good and bad, of copper pour segments on signal layers of PCBs.

This new one-hour course will discuss and define:

  • Reasons to put copper pours on signal layers
  • Should copper pours always connect to ground?
  • Measured impact of pours on impedance of lines
  • Measured impact of pours on energy coupling
  • Measured impact of pours on power delivery
  • Impact of copper pours on PCB manufacturability.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 11:00 a.m.
9: That FPGA. We Need to Make a Quick Change! (Again)
Adam Taylor, Adiuvo Engineering & Training

FPGA designers often make PCB designers weep with our demands and late changes. It does not have to be this way, however. Working collaboratively together and understanding each other’s requirements, constraints and needs, we can achieve amazing designs that enable delivery on time, on quality and on cost.

FPGA are typically used on designs which are challenging, be it performance, system integration, security or safety. While these requirements are seen as driving the functionality of the FPGA, they also have an impact on the schematic design and, of course, the layout.

FPGA boards often bring a number of challenges, from clocking to high-speed memory interfaces (DDR4, etc.) to multigigabit serial links, pin allocation, and power and thermal demands. This session will begin to bridge the gap between the HW and FPGA worlds, demonstrating they are not as orthogonal as might at first seem.

The session is presented by an experienced FPGA and board designer, and will demonstrate how the FPGA and board designers can work together collaboratively from the concept stage.

Key elements:

  1. Understanding the FPGA development flow – what happens when and why.
  2. What constitutes an FPGA? The major building blocks (logic, IO, plls, etc.).
  3. Just how flexible are FPGA IO structures? Explore on-chip termination, digital controlled impedance, fine picosecond delays, etc. What are IO banking rules?
  4. How do we pin plan a FPGA project? What kind of pin swapping and IO banking can we swap to ease routing? What can the FPGA engineer provide and when (e.g., IBIS models)?
  5. How do we estimate accurately the power (and hence thermal issues) of the FPGA? Spreadsheets are one tool, but there are others such as power aware simulation.
  6. Power architectures – How we select and optimize the power architecture for the device, and what impact this has on thermal dissipation.
  7. Thermal management – How we determine heat sinking requirements, and what can be done to reduce this power dissipation (a lot more than you might think).
  8. Dedicated IO – how we handle them.
  9. Board bring up – What do we need to be able to bring up the board and decouple the risk from a new board and new application? This will look at elements such as on-chip ADCs, commissioning programs, JTAG approaches, decoupling technical risk with interfaces like DDR4, etc.
  10. What we can do when things do not go as we expected to recover the situation.

This session will be very interactive. The best way to learn is by seeing and demonstration, therefore, this talk will walk through and demonstrate several key elements of this codesign approach.

Who should attend: PCB Designer/Design Engineer, System Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
11:00 a.m. to 12:00 p.m.
12:00 p.m. to 1:00 p.m
Free Lunch on Exhibit Floor
1:30 p.m. to 3:30 p.m.
10: Designing Complex PCBs
Stephen Chavez, Siemens

Designing complex PCBs is a multifaceted and challenging task that plays a pivotal role in the development of advanced electronic systems. This presentation explores the key considerations, methodologies, and emerging trends in the field of complex PCB design. The complexity of modern electronic devices demands intricate PCB layouts to accommodate high-density components, diverse functionalities, and stringent performance requirements. We will delve into the critical aspects of layout solvability, signal integrity and electromagnetic interference, power integrity and power distribution, thermal management, and manufacturability, emphasizing the need for a holistic and systematic approach.

We will also address the incorporation of EDA tools to enhance the efficiency and reliability of complex PCBs. As the demand for smaller form factors and increased functionality rises, designers face the challenge of optimizing space utilization while minimizing electromagnetic interference and signal crosstalk. We will explore strategies for mitigating these challenges, including the use of automation in placement and routing to include simulation and DfM tools.

Furthermore, we will discuss the role of collaboration between hardware and software teams in achieving successful complex PCB designs. The integration of design for manufacturability (DfM) and design for testability (DfT) principles is highlighted as essential for streamlining the production process and ensuring reliability of the final product. The evolution of Industry 4.0 and the Internet of Things (IoT) introduces new dimensions to complex PCB design, with considerations for connectivity, security and adaptability becoming increasingly important.

In conclusion, this presentation provides a comprehensive overview of the challenges and strategies involved in designing complex PCBs, emphasizing the interdisciplinary nature of the task and the need for a holistic design approach.

What you will learn:

  1. The three key perspectives of success in PCB design
  2. Increase productivity and proficiency with current/future EDA software (automation)
  3. Benefits of implementing best practices and the cost of doing nothing (remaining status quo).
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
1:30 p.m. to 3:30 p.m.
11: PCB Design Techniques to Improve ESD Robustness
Daniel Beeker, NXP Semiconductor

We all are involved with developing products that generate, control, and consume electromagnetic field energy. This is not what we are taught. Circuit theory suggests that electrical energy is made up of electrons moving in the conductors. Switches add conductors, and the current instantly starts to move in the loop. The wires carry the energy, and the load instantly responds to the flow of energy. Wrong!

Switches add new spaces, and the moving field carries the energy. It takes time for the field energy to move into that space. The moving field energy has no idea of what it is at the end of the new space. Field energy moving through a space is the current flow. The magic here is the displacement current flowing through the dielectric at the wavefront, completing the circuit. Fields do all the work.

Current flow is a measure of moving field energy through a space. Current flow occurs in the space between the conductors that bound the dielectric. Some of the fields interact with the molecules in the outer surfaces of the conductors. This interaction consumes some of the field energy, hence a resulting voltage drop caused by this “resistance.” The consumption of field energy results in increased movement of the molecules, and hence is converted to heat! The dielectric also consumes energy the same way unless it is a vacuum.

Electromagnetic energy moves slower through a physical dielectric than through space. Field energy can only travel in space, not through matter. It takes time for the energy to go around the molecules it encounters. The higher the molecular density, the longer the path, hence, it takes the field longer to go from one place to another. Once created, EM field energy can only move from one space into another one as we intend, be converted into kinetic energy, or radiated into the surrounding spaces.

After an introduction to EM field behavior, and the concept of ESD and EOS, this course will describe several effective methods for designing the spaces which will increase the overall robustness and immunity of a PCB. These methods will result in a product with improved reliability. This presentation will give some simple definitions for ESD/EOS and describe the important differences in the energy involved and the type of damage that can result. PCB design techniques for improving system robustness will be presented.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
5:00 p.m. to 6:00 p.m.
Reception on Exhibit Floor, sponsored by EMA Design Automation
9:00 a.m. to 10:00 a.m.
F1: Controlling the Waves: A Field-based Perspective on High-speed PCB Design
Daniel Beeker, NXP Semiconductor

Good signal integrity and EMC start with a good PCB design philosophy. It is critical for design engineers to understand the behavior of EM fields. Proper design of the spaces these fields follow through the board is critical. Creating transmission lines that will meet the needs of the PDN and the fast-switching ICs in today’s high-performance products can be a challenge. Certain questions need to be answered to define the PCB geometry that will lead to a successful design. This seminar will present an easy-to-understand science-based approach for PCB design.

Attendees will leave this seminar with a better understanding of:

  • The basic behavior of EM fields as they move through the PCB and ways to control them
  • The most important characteristics of the ICs in the design that affect the PCB layout requirements
  • How to create an effective board stackup
  • How to use these characteristics to define the PDN component selection and placement, as well as the interconnects needed to create the transmission lines that support these requirements
  • How to use these characteristics to define the transmission lines that carry the high-speed signals.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate, Advanced
10:00 a.m. to 11:00 a.m.
F2: AI and PCB Design: Where are We and Where are We Going?
Matthew Leary, Newgrange Design

“There is much talk about how AI will be impacting our future. This presentation will pull together some of the current thinking about AI from different industry experts with the goal to provide PCB designers information and hopefully some guidance about how we expect AI to impact PCB design in the two-, five- and 10-year timelines.

Key topics to cover:

  • Define/distinguish among automation, AI, generative AI, LLMs
  • The latest thinking on AI from major CAD players like Altium, Mentor (Siemens), Cadence, and Zuken
  • How AI will affect the day-to-day work of the PCB designer
  • Does AI pose an existential threat to the profession of PCB design?
  • How today’s PCB designer can best prepare to be ready for the changes that AI will bring to the industry
  • The problem of protecting IP in an AI environment.

It is important to note that this is a speculative talk based on some of the latest information available. Information about AI is changing rapidly. Some companies are willing to disclose only certain things that they are working on to the public. The goal is to educate and try to shed light on this rapidly developing, important influence to our industry with the intent that this will help us all take a step forward together to make good decisions about our careers and how we will best integrate new tools and features into our work to get optimal productivity and career gains.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
11:00 a.m. to 12:00 p.m.
12:00 p.m. to 1:00 p.m
Free Lunch on Exhibit Floor
1:30 p.m. to 2:30 p.m.
F3: Precision in Design: A Course on Strategic Design PCB Assembly
Tomas Chester, Chester Electronic Design

Effective printed circuit board (PCB) design extends beyond the meticulous consideration of layer stackup and appropriate PCB materials; it equally hinges on the strategic integration of assembly elements. Recognizing the pivotal role that assembly processes play in the manufacturability of a board, this course provides participants with a comprehensive understanding of the intricacies of assembly procedures. By immersing attendees in the nuances of the assembly process, this training empowers them to adeptly navigate the feedback loop, thereby guaranteeing the triumph of present and forthcoming designs.

The course will delve into the following aspects of assembly:

  • Small components and stencil requirements
  • Designing with thermal relief and why
  • Typical assembly issues and how designers can fix them.

This course will impart theoretical knowledge and reinforce learning through practical application. With instances of failures and conducting in-depth analyses of their root causes, participants gain valuable insights into preemptive strategies. Armed with this knowledge, they will be able to proactively mitigate potential issues, ensuring a resilient and successful approach to their current and future designs.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
2:30 p.m. to 3:30 p.m.
F4: Training the Next Generation of Designers
Kristen Aguiar, Altium

It’s become increasingly obvious that, as an industry, we are running out of PCB designers. As the current generation of PCB designers begins to retire in greater numbers, the problem will only get worse with time. Who will take over as we continue to lose more and more highly experienced designers? This presentation will discuss the importance of focusing on the next generation of designers and how to train them in a way that will resonate with a younger generation.

Current challenges:

  • Lack of awareness of PCB design as a possible career option
  • Limited training opportunities
  • Increasing complexity leads to less capable self-taught designers
  • Limited pipeline of new designers
  • Current generation of designers is retiring.

What we do now to train new designers:

  • Training on the job
  • Transfer/cross-training EEs to do design work
  • Outsourcing
  • Educational programs.

Tips for training younger candidates:

  • Find the right candidate (what makes a good designer, how to find those skills in the next generation)
  • Training for both software competency and good PCB design practice, at the same time
  • How to build skills quickly
  • How to keep engagement and avoid losing potential new designers
  • What do new designers want for job satisfaction (will include interviews, quotes, etc.).
Who should attend: PCB Designer/Design Engineer, CEO/COO/Sales/Marketing
Target audience: Beginner
4:00 p.m. to 5:00 p.m.
F5: Smart PCB Design and Surface Finish: Sustainable Solution for Automated and Optimized Cu Balancing and Electroplating Steps
Agnieszka Franczak, Elsyca NV

PCB manufacturing relies on building a physical PCB from its design, accounting for a set of required specifications. Understanding the design specs is crucial as it has a direct impact on the PCB’s fabrication process, performance and productivity yield rate. One such spec of interest is copper balancing: copper traces distribution in every layer of the PCB stack-up, which provides exceptional electrical and thermal characteristics necessary for signal transmission and heat dissipation.

If the copper distribution is uneven, mechanical misalignments such as board twists, bow or warpage can occur. Thus, one of the tasks a PCB designer performs is to balance the copper trace distribution so mechanical properties can be improved. An optimized copper balance also ensures homogenous copper plating across each PCB layer, creating uniform copper layer thickness on the plated surfaces. This in turn, improves signal transmission and overall PCB performance, provides consistent PCB thickness during lamination and reduces the risk of low-pressure surface areas that may result in redesign.

Copper electroplating plays an extremely important role in PCB manufacturing and its major advantage is to reduce the ground line impedance and voltage drop. The process performance directly affects the quality of the copper layer and related mechanical properties: in acid copper plating, the challenge is to achieve proper thickness distribution and surface uniformity without unduly compromising metallurgical properties, such as percent elongation and tensile strength of the deposit. Reducing current density can equalize the copper thickness to some extent, but leads to an inordinate increase in the overall plating time, affecting the throughput of PCBs drastically. Therefore, the proper control of the process performance and consequently, the quality of the electroplated copper layer, are both important parts of the PCB plating technique, which remains one of the challenging processes even for relatively experienced PCB factories. Thus, it seems that an upfront recognition of the plating process performance in terms of the copper layer coverage and thickness would add a great value to the proper process design and control.

With the recent computer simulation technology development, PCB designers can now perform fully automated and optimized copper balancing activities, ensuring designs are free of redesign risks and fabricated toward required copper distribution and thickness specs. Furthermore, the copper balancing tool can be integrated within their design business logic.

This talk will highlight issues caused by poor copper balancing at the design stage, a mitigation strategy to address the issues, and the workflow of the integration process, which creates a smart design. The concept of a digital twin of the copper plating process in PCB manufacturing and the use of a computer-aided analysis approach for a quick assessment of the under- and over-plated surface areas, and their further mitigation toward required thickness tolerances will be discussed as well, as it is aligned with Industry 4.0 and smart manufacturing concepts.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test Engineer, Fabricator Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
4:00 p.m. to 5:00 p.m.
F6: Quality Optimization through Accuracy and Force Validation
Michael Sivigny, CeTaQ Americas

If you don’t measure, you don’t know. These are appropriate words for the application of statistical methods for measuring machine and process capabilities in surface mount technology (SMT) manufacturing.
Only through diagnostic measurement and analysis of SMT equipment can quality performance improvement be realized. Measured mean values can be used to “soft” calibrate machines to a higher level of accuracy than available through OEM standard calibrations.

With the complexity of high-speed automation combined with high accuracy requirements for product miniaturization, it is necessary to dig deeper with statistically significant data collection methods to understand and solve the root cause of sub-component machine failures which impact product quality.

When machines are permitted to run in “maximum accuracy mode,” they are more confident and capable of producing today’s high reliability electronics with fewer defects. Defect contribution in each process step needs detailed analysis to reduce cost. When costs are minimized, the underlying inherent process efficiencies go way up which contributes to higher productivity and bottom-line profitability. The improvement effects of process optimization have a number of intrinsic benefits that can easily maintain high manufacturing productivity.

This presentation discusses individual process step validation methods with real examples of improvement that contribute to DPMO reduction. Examples will include:

  • Laser marking: Understanding trends and correction methods to improve accuracy performance
  • Stencil printing: The characterization considers accuracy of the alignment system, dynamic measurement of print force and Y snugger board clamping force
  • Dispensing: Highlighting the importance of correctly functioning fiducial alignment
  • Placement accuracy and placement Z-force: Both are looked at to calibrate head/angle offset associations and dynamically check individual spindle forces and energy dissipation.

While each process step is characterized, the underlying objective is to verify OEM specifications and prove that machines are capable for intended quality performance. This allows engineers to streamline efforts and focus on other areas of improvement.

Who should attend: Assembly Engineer/Operator, CEO/COO/Sales/Marketing
Target audience: Beginner, Intermediate, Advanced
4:00 p.m. to 5:00 p.m.
F7 : Flex Design for Beginners
Lauren Waslick , Newgrange Design

“Venturing into the world of flexible circuit design might seem intimidating if you have only designed rigid boards in the past. While flex design does have important differences to be aware of, many of the basic principles are the same. As a designer, it is important to understand how they are different and where the key differences fall in the design process. The goal of this presentation is to provide guidance on what to watch out for in each step of the design process when designing a flex board for the first time.

Key topics to cover:

  • Different types of flex boards: flex, rigid-flex, flex with stiffener
  • Importance of early flex fabrication house involvement: stack-up, rules, cost
  • Stack-up considerations: material choices, layer count flexibility
  • Mechanical considerations: bend lines and radius, stiffener regions
  • Design considerations: footprint modifications, placement guidelines, routing suggestions
  • Additional design rules: keepouts around transitions, controlled impedance
  • Output files: fabrication drawing details, folded STEP models.

What you will learn:

  • The most important differences between rigid and flex design
  • Critical questions to ask early in the process
  • Collaboration between electrical, mechanical, design and manufacturing early in the process to come up with cost-effective and creative solutions.
Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Beginner, Intermediate
5:00 p.m. to 6:00 p.m.
Reception on Exhibit Floor, sponsored by EMA Design Automation


9:00 a.m. to 11:00 a.m.

Opening Remarks

Gene Weiner, Weiner International Associates

U1: The Dawn of a New Interconnect Era: Redefining PCB Technologies for Tomorrow

Dana Korf, Nano Dimension

Printed circuit board interconnect density has historically been driven by part packaging requirements. Component size and I/O pitch interconnect density has been driven by the circuit board available manufacturing technologies and available materials. Design rule requirements are started by designers which are used to develop materials and process innovations.

Confounding the technology implementation is the conservative nature of the industry to use innovative technologies before industry standards are developed. Typically, an application arises where the product form factor or performance requires its volume introduction prior to industry standards release. High density processes typically initiate in component packaging then migrate to larger form factors. This is the current state of UHDI technologies.

This presentation will review PCB standards up to Ultra HDI (UHDI) and printed electronic technologies such as additively manufactured electronic (AME) technologies. PCB standards are generated by experts in their field that merge requirements from differing industries and applications to create a common set of requirements and test methods. Industry standards do not positively impact production yields or cost. They focus on product reliability and availability. The presentation will discuss existing and developing standards, use, and gaps.

A solution for resolving the data transfer quality issues that are needed for these newer technologies will also be presented.

U2: New Materials for UHDI and Substrates

Paul Cooke, Ventec

In the past few years there have been concerns in the industry especially in products requiring high-reliability when using microvia  structures.  As result, many fabricators have mandated push-back  on  very complex and high-layer-count designs. 

This has resulted in very conservative rules for designers to use to fabricators’ capabilities. Some fabricators have also struggled to ensure even simple structures are built reliably and with repeatability.

This has raised concerns as we move to Ultra HDI structures requiring smaller geometries and features. This presentation looks at materials that ensure that smaller and more complex structures can be built reliably. 

Thinner dielectric layers have been developed for build-up multilayer but can cause issues with resin movement caused by spread glass and higher resin-to-glass ratios for the manufacture of reliable stacked microvias. 

Current industry practice has been to limit designs to staggered vias or 1-2 layers of stacked microvias. This talk shows how a thin non- reinforced dielectric layer can be used and optimized for stacked microvias that demonstrates solid thermal reliability up to 6 layers of HDI, it also shows there seems to be no indication yet of a ceiling on how many layers could be used.

U3. Novel Dielectric Build-Up Material for Advanced Packaging
Jason Rouse, Ph.D., Taiyo

The relentless pursuit of miniaturization and performance enhancement in electronic devices necessitates the development of innovative dielectric materials. Taiyo is introducing a novel dielectric build-up material engineered to meet the evolving demands of advanced electronic applications. Key attributes include exceptional dielectric constant, low dielectric loss, high thermal stability, and superior mechanical flexibility. These characteristics make it ideally suited for integration into high-frequency communication devices, advanced capacitors, embedded passives, and other miniaturized electronic components.

The dielectric build-up material offers substantial improvements in signal integrity, power efficiency, and reliability, paving the way for next-generation electronics. Furthermore, its compatibility with existing fabrication processes ensures seamless adoption within the industry.

This talk encapsulates the transformative potential of the proposed dielectric material, heralding a new era of innovation in electronic engineering.  

11:00 a.m. to 12:00 p.m.
12:00 p.m. to 1:00 p.m
Free Lunch on Exhibit Floor
1:30 p.m. to 5:00 p.m.
U4: New Printable Materials for Additive and iSAP Processes
Mike Vinson, Electroninks

Utilizing conductive inks alongside traditional metallization methods in Ultra-High-Density Interconnect (UHDI) applications aims to enhance design flexibility, functionality, and cost efficiency through additive manufacturing. This approach ensures that performance and reliability standards are maintained without compromising on these crucial factors.

Conventional metallization techniques such as physical vapor deposition (PVD) and electroless plating involve complex multi-step processes with inherent limitations. These limitations encompass constraints related to panel area, uniformity on intricate 3D shapes, temperature sensitivity, environmental concerns, and economic considerations such as throughput, capital expenditure (capex), footprint, maintenance, material wastage, and energy consumption.

An emerging trend in the industry involves the adoption of jettable or sprayable conductive inks for semi-additive (iSAP), conformal shielding and additive, 3D metallization. This shift offers significant advantages in terms of total cost of ownership and throughput. Ink-based processes eliminate the need for vacuum conditions and operate at relatively low temperatures, typically at or below 180°C, making them more efficient and economical alternatives. Metal complex conductive inks can be applied using various digital printing methods like aerosol jet printing, inkjet printing, and spray coating, offering versatility across substrates such as 3D packages, wafers, chips, boards, and housings, while ensuring high-performance shielding at a reasonable cost with exceptional reliability for the semiconductor packaging industry.

U5: Direct Exposure for 6 Microns and Beyond Features

Dennis Pusch, Schmoll

To create finer lines and spaces, the machine platform itself needs to fulfill a number of requirements as along with higher resolution, higher accuracy demands come hand in hand.

Market trends and new requirements from various industry areas (PCB, substrate, even semicon) play a significant role to an equipment manufacturer in determining the path forward in their product development.

UHDI can be understood as the threshold where mils become microns.
Existing direct imaging (DI) equipment is laid out to address the manufacturing needs of today’s products, providing the required resolution with desired throughput. Stepping into UHDI territory, mutual dependencies of new equipment and process requirements along with new materials must be acknowledged.

This presentation will highlight the advancements in direct exposure, coming a long way from its “standard” resolutions down to 15, 8 or 6 microns (or even below), focusing on the developments in the light source and imaging technology itself, but also the interdependencies between equipment capabilities and existing processes aimed to evolve towards generating finer structures and features.

Miniaturization as determined goal comes only as a result from understanding the suitable match of correct imaging technology, choice of material and proper process adjustments in the pre- and post-processes.

U6: New Emerging Technologies & Plating Processes for UHDI Circuit Fabrication

April Labonte, Uyemura USA

The demands for more complex PCBs are here, requiring the ability to increase functionality while decreasing size. These requirements make the design of high-density interconnect PCBs important to the future of the electronics industry. Meeting these design demands requires an increase in performance for existing manufacturer processes while also looking toward the future of manufacturing capability. This presentation will touch on the technology requirements needed including a thin uniform seed layer with good adhesion and reliable connections. The presentation will then go over some emerging technologies including an adhesion promotor for semi additive process, palladium direct plate process and electroless copper capabilities.

U7: Additive Manufacturing of PCBs – Today’s Possibilities with Inkjet Printing and Tomorrow’s Potential with Hybrid Electrohydrodynamic Printing

Celia Wenzler, Notion Systems

One of the founding ideas of Notion Systems was to replace the current subtractive process chains with additive process steps in electronics manufacturing. Inkjet and electrodynamic printing (EHD) are two key technologies that Notion Systems has implemented in a platform optimized for high throughput mass production. The platform is used to produce electronic displays, printed circuit boards, semiconductor components, as well as high-precision optical 3D parts, covering the full range of solutions from laboratory to production.

While the inkjet platform is already being used in mass production today, EHD technology will soon be scaled up to prepare for the submicron mass production of the future. Patterning is easy to implement with inkjet printing, as it is a digital printing process with drop-on-demand functionalities. Typical inkjet line spacings of 50μm cannot fulfill the ever-increasing demands on HDI boards and IC substrates. Inkjet reaches its limits with smaller structure sizes, for example, and this is where EHD technology comes into play.

EHD printing is a new high-resolution printing technology that enables maskless, contactless, conformal and additive structuring in the micrometer range. Compared to conventional inkjet printing, EHD technology outperforms inkjet printing by two to three orders of magnitude with possible structure sizes of < 1μm.

The combination of the individual technologies represents an opportunity to unite the advantages of both processes. The limitations of inkjet printing are overcome in hybrid printing with EHD. The smallest structure sizes, which are far below the resolution of inkjet, can be processed with EHD. At the same time, inkjet printing complements its strengths and is ideally suited for larger structure sizes and large-area coatings. The advantages and disadvantages of both processes have led to the concept of a hybrid machine.

In summary, it can be said that hybrid printing can represent a unique solution for high-performance electronics, semiconductors and other applications in the future. It paves the way for additive printing in applications dominated by photolithographic microfabrication and enables completely new components made from microscale building blocks.

U8. Preparing to Produce UHDI 

Hardeep Heer, FTG

Ultra-high-definition interconnect (UHDI) technology represents a significant leap forward from high-definition Interconnect (HDI) technologies. UHDI technologies deal with sub-25-micron designs. There are manufacturing processes such as m-SAP which have been used for manufacturing handheld devices, however, this process is limited to designs with 30 microns and above. Some new patented processes such as A-SAP, additive bond films (ABF) and copper sputtering are being explored to address sub-25-micron designs. These processes will need extensive capital investment and will require R&D resources to bring them to mainstream production.

This presentation will investigate challenges faced in deploying UHDI technologies. The challenges include new manufacturing equipment, manufacturing processes, available materials and the cost of developing UHDI designs. It will present a brief introduction to these processes, along with the cost associated with UHDI manufacturing.

U9: Panel Discussion

Stephen Chavez, Siemens Digital Industries Software; Anaya Vardya, American Standard Circuits; speaker to be named, KLA 

5:00 p.m. to 6:00 p.m.
Reception on Exhibit Floor, sponsored by EMA Design Automation
9:00 a.m. to 12:30 p.m.
12: Designing the Signal Return Path
Susy Webb, DesignScience

When designing a PCB, the signal routing and its return are critical to the circuit working properly. Great care is usually given to routing the signals, but often the return portion is the last thing considered, and sometimes it is forgotten altogether.

Key topics to cover:

  • Designing the signal return path and physics involved
    • Where and how energy flows
  • The interference caused when it is not controlled
  • Planes and stackup that will be needed.
  • Best ways to contain energy fields
  • Spacing that helps prevent problems
  • Routing and return movement when the signal flows from layer to layer.

Throughout, we will discuss some signal routes and look at the paths that might set up the best possibility for a clean return.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 12:30 p.m.
13: Demo Man
Christopher Young, Young Engineering Services LLC

The goal is to demonstrate hands on physical characteristics of good and bad PCB design implementations through a set of controlled hardware demonstrations. The attendees would also gain knowledge and experience with how to use instrumentation to verify PCB design characteristics.

Key topics to cover:

  1. Via type and placement when transitioning between layers.
  2. Power plane spacing and power plane impedance over frequency.
  3. Heat dissipation techniques – Heat pipes, vias, heatsinks (material matters).
  4. What ferrite beads do, and their effect in a PCB design.
  5. Show the physical force effects of pogo pins on a PCB.
  6. Demonstrate what a standing wave looks like on an oscilloscope.
  7. Show what crosstalk looks like on a scope.
  8. Poll attendees for ideas and demonstrate something they would like to see. This would need to be done in advance of the conference and meet feasibility and safety standards.

Attendees will leave the session with the confidence and practical methodologies on how to use laboratory test equipment to verify physical PCB design characteristics.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer, Test Engineer
Target audience: Beginner, Intermediate
9:00 a.m. to 6:00 p.m.
14: How PCB Design Affects Fabrication
Paul Cooke, Ventec

This course will walk the audience through the entire multilayer PCB fabrication process, making stops along the way to explain how PCB design requirements affect the numerous fabrication steps and if/how the finished product can meet the intended quality and reliability requirements. A detailed explanation will be given for each of the process steps and how that step affects quality and reliability.

Key topics to cover:

  • Design requirements, with an explanation of the dos and don’ts of how they affect fabrication and impact yields
  • Process controls adopted by the fabricator to ensure maximum yields and quality are maintained during each step of fabrication
  • Pros and cons of variables available to the designer:
    • Solder mask
    • Surface finish
    • Materials selection
    • Copper weights
    • Feature size, etc.

The course also looks at fabrication drawing specifications and how they can affect yield, cost, quality and reliability.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator
Target audience: Beginner, Intermediate, Advanced
12:30 p.m. to 1:30 p.m.
Lunch-N-Learn (Thursday Conference Attendees Only)
Sponsored by PCB Technologies USA
2:00 p.m. to 4:00 p.m.
15: The Most Common Issue Seen in Incoming Designs in PCB Fabrication
Mike Tucker, Millennium Circuits, and Ray Fugitt, DownStream Technologies

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. Methods we will look at include netlist comparison, design for manufacturing, and design rule analysis. We also talk about proper documentation needed for PCB manufacturing. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will take back some knowledge to better assist them in using their existing tools in the market to produce better and more accurate designs.

Who should attend: PCB Designer/Design Engineer, Fabricator Engineer/Operator
Target audience:Beginner, Intermediate, Advanced
2:00 p.m. to 4:00 p.m.
16: PCB Thermal Design: Quenching the Blaze
Ethan Pierce, Pierce Design, and Tomas Chester, Chester Electronic Design

Amid the fast-paced advancements in PCB design, thermal consideration and thermal management of designs is of paramount concern. Engineers and designers are constantly seeking innovative ways to meet efficiency and reliability standards. This seminar aims to explain complex thermal theories and introduce practical approaches to optimizing PCB design for superior thermal performance. An examination and understanding of the design strategies and process to promote a performant and reliable system. This will be tied together with design examples and personal anecdotes.

Key topics to cover:

  • An explanation of heat transfer mechanisms: Conduction, convection and radiation, will establish a solid foundation in order to explore thermal management in PCB design
  • Introducing the process of the Thermal Design Engine and how it applies to your applications
  • Unveiling the process of preliminary thermal structuring, physical testing, and refinement of the system, illustrated through case studies.

Further, the seminar will delve into the diverse landscape of PCB materials and design strategies:

  • A comprehensive overview of IMS and Aluminum boards, shedding light on material selections, stackup configurations, and the mantra “Copper is Your Friend” in board design
  • An introduction to copper coins, their types, applications, and their important role in heat dissipation, complemented by a real-world high-power MOSFET design case study and a comparative analysis of a high-power MOSFET with and without a copper coin
  • A showcase of simulations reflecting the impact of conductive vs. nonconductive fill vias in thermal management.

The discussion explores simulations on thermal performance with a comprehensive simulation, evaluating the thermal performance of the discussed design strategies, and integrating learned concepts into system design.
What you will learn:

  • Real-world examples and hands-on experience with various thermal management strategies
  • Techniques for effective thermal simulation, analysis, and integration into their PCB design workflow
  • Insights into collaborative frameworks that foster innovation in thermal management, de-risking designs, increasing the likelihood of success and reliability.

Join us to demystify the intricacies of thermal management in PCB design, and propel yourself

Who should attend:PCB Designer/Design Engineer, System Designer, Hardware Engineer, Test, Engineer, Fabricator Engineer/Operator
Target audience:Beginner, Intermediate
2:00 p.m. to 6:00 p.m.
17: PC Board Design for Power Distribution and Decoupling
Rick Hartley, RHartley Enterprises

The majority of EMI problems are caused by poor design of the power distribution network (PDN), as are a large percentage of signal integrity issues. Proper power distribution is the foundation around which all things work in the circuit. If this structure is not designed correctly the entire circuit is at risk from noise and signal integrity issues, as well as a high probability of EMI concerns. Low impedance in the power distribution network, across the harmonic frequency range of a digital circuit, is critical. Many subtle PCB layout techniques have a major impact on correct power bus design.

This 3.5-hour course (new to PCB East) will discuss and define:

  • Impedance of vias, planes and mounted inductance of capacitors
  • Energy delivery to IC cores and impact of IC pin out on bus impedance
  • Placement of decoupling in moderate- and high-layer-count PCBs
  • Multiple capacitor values and how to resolve anti-resonant peaks
  • Effect of ferrites in the power bus in digital and analog circuits
  • Importance of power/ground plane pairs and impact of ultra-thin pairs
  • Extreme importance of PCB stack-up for best power delivery.
Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
4:30 p.m. to 6:30 p.m.
18: The Benefits of Grid Systems in Complex Board Design
Susy Webb, DesignScience

When a board is designed without uniformity, there can be part footprints that do not match, part placement that does not permit good trace spacing, signal fanout that is blocked by random via placement, and routing channels that do not permit consistent number of traces.

Using grid systems can have some great benefits and can help make challenging boards possible. They can help with the symmetry of placing parts, and keeping them in alignment so that the parts don’t encroach into routing lanes. Using a gridded pattern for through-hole and HDI fanout vias helps get more signals out of large parts, permitting more complete fanout possibilities, and can also help set up an effective return path. A good routing via grid can set up the maximum number of signals flowing through the open areas on any layer, and can help with some spacing, heat, and manufacturability issues as well. In this presentation we will talk about each of these grid systems and more, and show ways to implement them to make designing a complex board more efficient.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Beginner, Intermediate
9:00 a.m. to 11:00 a.m.
20: Differential Pair Routing for SI and EMI Control
Rick Hartley, RHartley Enterprises

Differential Pairs have been used in PCBs for many years to carry high-speed serial and some high-speed parallel data, in a variety of bus formats. Many board designers and engineers believe the rules for differential pairs are the same in a PC board as they are in a cable or a twisted wire pair. This is usually not the case!

This two-hour course (new to PCB East) will discuss and define:

  1. Characteristics of differential pair lines
  2. Impact of line-to-line spacing on signal integrity
  3. Line length (timing) matching: how tightly?
  4. Impact of crosstalk on differential pair behavior
  5. Issues that cause timing skew, including fiber weave
  6. Best differential pair line termination schemes
  7. Impact of changing layers with differential pairs.
Who should attend: PCB Designers/Design Engineers, Hardware Engineers, System Designers, SI Engineers
Target audience: Beginner, Intermediate, Advanced
9:00 a.m. to 11:00 a.m.
21: Watt’s Up with Wearables: Navigating the Circuit of IEC 60601 Compliance
Shrouk El-Attar, Shrouk El-Attar Consultancy

The journey from concept to market for TE devices is laden with intricate regulatory challenges, especially concerning compliance with the IEC 60601 standard. This workshop is designed to help navigate the maze of regulations and standards that govern the safety and efficacy of medical electronic wearables. The workshop aims to equip attendees with the necessary knowledge and tools to successfully navigate the complexities of IEC 60601 compliance using practical examples.

What we will cover:

  • Introduction to medical wearables and IEC 60601 compliance
  • Collaborative mock design of a smart health monitoring wristband
  • Risk management and safety analysis in line with ISO 14971
  • Practical insights into electrical, mechanical, and software safety requirements
  • Navigating electromagnetic compatibility (EMC) in wearable devices
  • Real-time mock compliance review of the designed wristband.

What you will learn:

  • End-to-end process of designing a compliant Smart Health Monitoring Wristband
  • Practical application of IEC 60601 standards in wearable technology
  • Risk assessment and mitigation strategies specific to medical wearables
  • Navigating regulatory submissions with a focus on FDA 510(K) and EU MDR.
Who should attend: PCB Designers/Design Engineers, System Designers, Hardware Engineers, CEO/COO/Sales/Marketing
Target audience: Beginner
9:00 a.m. to 12:30 p.m.
22: Signal Integrity in Thin PCB Materials and IC Substrates
Zachariah Peterson, Northwest Engineering Solutions

HDI and UHDI designs push the limits on layer thickness in conventional materials. Thinner low-Dk materials have also enabled much higher layer counts without HDI manufacturing requirements, but the impacts on SI, PI, and EMI are not always understood. Due to the interplay between line width, allowable line spacing from an SI perspective, Dk value, and layer thickness, it is important to understand how signal behavior is altered when designs are pushed into thinner materials.

This presentation will show how thinner materials and their Dk values affect signal integrity, as well as what designers can do to hit SI targets by balancing Dk, copper roughness, and laminate thickness. These trends will be discussed in terms of HDI/UHDI PCBs, but the same trends are seen in IC substrates, and the implementation of those practices for more advanced PCBs will be discussed to illustrate how to support bandwidths up to 56GHz. Topics to be presented will include:

  • An explanation of the trend toward lower Dk in terms of line width/spacing densities
  • How Dk and layer thickness affect single-ended crosstalk and differential crosstalk
  • How thick low-Dk materials vs. thin moderate-Dk materials affect signal integrity
  • How routing and via structures in HDI/UHDI PCBs and packaging affect signal integrity and available channel bandwidth
  • Examples showing how Dk and layer thickness are used to enable broadband transmission in single-ended nets, RF nets, and differential nets.

Simulation examples from real designs will be presented to illustrate the design tradeoffs listed above, and implementation in real designs will be shown as examples. Designers will learn how to balance tradeoffs among Dk value, Df value, copper roughness, and laminate thickness when selecting stackup materials based on the frequency range that is important in their systems.

Who should attend: PCB Designer/Design Engineer, SI Engineer
Target audience: Intermediate, Advanced
9:00 a.m. to 12:30 p.m.
23: Principles of Building a PCB Stackup
Susy Webb, DesignScience

The stackup of a printed circuit board is one of the most important parts of the design layout. It affects the way the signals flow on the board, so it can affect many other aspects of the functioning board, like impedance control, return current and the amount of crosstalk, common mode currents, and displacement currents. In today’s higher-speed designs, it is critical to do this step well. We will discuss what is needed for a good stackup, and the routing thereon, both from an electronic and a manufacturing perspective.

Who should attend: PCB Designer/Design Engineer, System Designer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
12:30 p.m. to 1:30 p.m.
Lunch-N-Learn (Friday Conference Attendees Only)
Sponsored by DownStream Technologies
2:00 p.m. to 4:00 p.m.
24: PCB Layout of Switch Mode Power Supplies
Rick Hartley, RHartley Enterprises

Having a solid understanding of SMPS printed circuit board layout can eliminate SI and EMI problems. Switch mode power supplies have five circuit loops, all of which are important, but a couple of the loops are critical. An improperly designed switch mode supply will often have EMI problems or not function as intended, in some cases will not function at all. Understanding what makes up a switcher circuit and knowing how to take care of the loops during PCB layout will permit these supplies to operate flawlessly, with very high efficiency, and without EMI issues.

This two-hour course (new to PCB East) will discuss and define:

  • Basic operation and EMI concerns of SMPS circuits
  • Self-contained SMPS controllers, good and bad
  • PCB layout of critical circuit loops, including feedback
  • Proper grounding on one- and two-layer vs. multilayer PCBs
  • Should ground be opened under “switch node” and/or inductor?
  • Good and “not good” EMI control techniques.
Who should attend: PCB Designer/Design Engineer, System Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced
2:00 p.m. to 4:00 p.m.
25: Heat Management Strategies through Better Layout
Syed Ubaid Ali Warsi, Wavetroniks

With continuous technological developments, electronic circuits are not only becoming faster and smaller but also more power-hungry. Consequently, related thermal issues are more prevalent than ever because most modern PCBs consist of numerous high-power components such as high-performance processors, transceivers, MOSFETs, and high-power LEDs, leading to excessive heat. Additionally, power conversion circuitry, including DC-DC converters and regulators, contributes significantly to temperature elevation and hotspots.

Besides the components, the resistance of the electrical connections, copper traces, and vias contribute to heat, and power losses. Thermal stress stands out as a primary cause of circuit malfunction, resulting in performance degradation or even system malfunction or failure. To address thermal stresses at the layout level, PCB designers must incorporate effective techniques to reduce heating impacts. This includes careful material selection, strategic component placement, power ground plane construction, thermal vias, and more. This presentation will explore these effective strategies and tricks that layout engineers can adopt to identify and mitigate major hotspots, ultimately enhancing the thermal performance of PCBs.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer
Target audience: Beginner, Intermediate
2:00 p.m. to 4:00 p.m.
26: High-Frequency Layout: Best Practices for PCBA Design
Gerry Callahan, Pentair

Circuit board assemblies today include more high-speed circuitry than ever before, making it difficult to meet all requirements, perform robustly in real-world conditions, and pass agency tests such as FCC.
Key topics to cover:

  • Why every design needs to consider high-frequency layout
  • Why EMI (electromagnetic interference) and SI (signal integrity) matter
  • Compare circuit theory and wave theory
  • Learn the difference between ground and return
  • Common problems and how to avoid them.

We will also see how this impacts agency testing (and how to pass the tests!), and discuss some recommended PCB stackups. Audience discussion is encouraged, and there will be time for questions and answers.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer
Target audience: Beginner, Intermediate, Advanced