Interconnect stress testing (IST) is a method to assess the reliability of microvias in printed circuit boards. Additionally, for a better understanding of the failure mechanisms, the IST fail specimen are prepared by beam etching sample preparation technique and analyzed by scanning electronic microscope (SEM) and electron backscatter detection (EBSD).

A failure or significant increase in resistance rise during the test indicates defects in the interface. These defects are most often caused by structural failures in the top or bottom section of the microvias at the metal-to-metal interface. The interconnect stress test is utilized to identify manufacturing issues with the via interface of PCBs. Specific manufacturing defects result in distinct IST curve shapes. While some curves display a straightforward rise, others demonstrate an exponential behavior.

This investigation focuses on analyzing the various curve shapes observed in IST tests, aiming to link these shapes to specific failure modes and related causes at the metal-to-metal interface. The objective is to determine which types of failures create specific IST curve shapes. Common failures include contaminants such as dirt and laser residues between the microvia and the copper, which weaken the connection and increase the resistance measured in the test.

This session will focus on the challenges posed by using HDI vias, from the perspective of layer transitions and power delivery. The example will be using a 12-layer PCB to discuss the requirements for signal layer transitions. Via stackups will be defined to enable good signal integrity. Power delivery and the via structures necessary will also be addressed. A must-see class for anyone planning to use this technology.

Shielding is a topic that seems so simple, yet yields so much confusion. From board level shields to enclosures to cabling, there are a lot of different ways to implement shielding – and some can make EMI problems worse.

This 3.5-hour presentation will go over the fundamentals of shielding for EMI, covering kHz – GHz ranges. We’ll talk about the mechanisms in play when different structural or board layer elements are combined with the goal of reducing EMI radiated emissions. We’ll get to the bottom of how to terminate cable shields.

You will learn:

• How different shield configurations interact with electromagnetic fields
• Different ways to evaluate shielding effectiveness
• Considerations for implementing shielding at the board, enclosure and cable levels
• Case studies of poorly and well-implemented shielding.

There is running debate among many design engineers about the use of copper pour segments in/on some layers of PCBs. Some say copper pours can increase crosstalk, change impedance of transmission lines, increase EMI, or have an impact on power delivery, etc. Others say that the opposite is true. This session will discuss the real impact – good and bad – of copper pour segments on signal layers of PCBs.

This one-hour course will discuss and define:

• Reasons given to put copper pour on signal layers
• Should sopper pours always connect to ground?
• Measured impact of pours on impedance of lines
• Measured Impact of pours on energy coupling
• Measured Impact of pours on power delivery
• Impact of copper pours on PCB manufacturability.

EMI occurs because some mechanical structure, within or attached to a system, is capable of resonating and radiating stray electromagnetic field energy. Those mechanical structures can be a cable attached to the enclosure, items near the circuit, a part of the metal chassis, a slot in the chassis or a portion of one of the circuit boards in the system. Knowing how to control these structures so they are not capable of resonance and radiation is the key to success.

This course will discuss and define:

• Determining max frequency of a system
• Antenna “in” and “on” PCBs and enclosures
• Metal vs. plastic enclosures and shielding of circuits
• Impact of slots and openings in enclosures
• Impact of component placement and PCB shape
• Extreme importance of I/O connector placement
• Correct shielding of I/O cables”

Why does the topic of library management dominate so many discussions today? The need for a good library system has been around since the dawn of PCB Design X years ago. Yet, for an industry that has existed for so long, how can it be that the creation, storage and usage of symbols and footprints seems like such an unsolvable problem? We all know what we want: to open a library, find the component quickly and easily with full confidence that component is correct and usable. And yet it seems like this is often out of reach.

What library systems exist and why do the choices we make so often seem to lead to a mess? Why choose one system over another? What works, what doesn’t, and why is there no universal system that works for everyone?

There is a lot of talk about how AI will be impacting the future of PCB design. This presentation will pull together some of the current thinking about AI from different industry experts with the goal to provide PCB designers information and hopefully guidance about how we expect AI to impact PCB design in the two, five and 10-year timelines.

In addition to AI, other trends need attention, ranging from manufacturing changes to supply-chain developments that will impact the industry. The goal is to provide a snapshot of what designers need to be prepared for to stay on top of our craft.

Ultra-high-density interconnect (UHDI) technologies are rapidly transforming the landscape of electronic systems by enabling the development of compact, high-performance devices. This presentation delves into the design and verification of UHDI topologies, an advanced technology that permits significantly higher wiring densities in electronic circuits. It covers essential design considerations such as signal integrity, thermal management, and material selection, while emphasizing the need for early collaboration with PCB fabricators. The industry best practice design process integrates advanced materials, high-speed interconnect strategies, and multilayer PCB architectures to achieve optimized performance and scalability. We’ll also discuss the importance of EDA tools for optimizing layouts, simulating signal integrity, and highly emphasize performing design rule checks. Various verification techniques and methodologies include simulation-based validation, electrical and thermal analysis, physical prototyping as well as mechanical stress testing, are explored to ensure UHDI reliability and compliance with industry standards.

Additionally, this presentation highlights emerging trends like AI-driven design optimization and machine learning (ML) EDA tools, and innovative manufacturing processes, positioning UHDI technology as crucial for the future across industries like consumer electronics and aerospace. By analyzing the challenges, EDA tools, and methods involved, the presentation provides a comprehensive understanding of the evolving UHDI design and verification landscape. Through this framework, attendees will gain insights into the efficient design and robust verification of next-generation UHDI topologies, addressing the increasing demands of modern electronics in sectors such as telecommunications, automotive and consumer electronics.

What you will learn:

1. A better understanding of UHDI PCB designs
2. Key design considerations, including signal integrity, thermal management, material selection, and the importance of close collaborations with the fabricator
3. Emerging trends in UHDI technologies and the impact of miniaturization on electronic system complexity.

Right first time” is a goal we all aspire to, but how often does it really happen? Even when we follow layout rules as closely as possible (whether we developed those rules ourselves or followed vendor-supplied guidelines), problems creep into the layout that cause issues during lab testing and result in costly, time-consuming respins.

Why is that? We maintain there are two big contributors:

• We often don’t simulate what we actually build (even though we thought we did)
• We don’t verify ALL our serial channels after layout; we analyze a handful of channels and expect them to be representative of everything else.

In this presentation, we’ll dig into these two issues and show how to address them.

We’ll start with a discussion about how the small details of board fabrication plating layer thickness and conductivity, or metal roughness on core vs. prepreg layers, can significantly impact design performance. It’s critical to model a board as it will be manufactured, instead of modeling it as you wish it could be manufactured. We’ll show how to evaluate PCB tradeoffs and create a detailed board model that ensures that the detailed design simulations performed reflect the behavior of the actual board.

Next, we’ll discuss post-layout verification and how to verify operating design margins for all the serial channels, instead of just a select few. We’ll look at traditional methods for performing post-layout analysis and see how they sharply limit the number of channels that can be verified. We’ll discuss what it takes to create an automated analysis methodology and how it can be coupled with protocol compliance analysis (e.g. PCIe-5) to assess a design’s operating margins. Finally, we’ll look at what it takes to scale that process up to a full-system level, using a current server-class dual-socket motherboard design as an example.

What you will learn:

• How PCB manufacturing impacts signal integrity
• How to ensure the stackup accurately represents the board-as-manufactured
• Why traditional post-layout verification limits analysis to a handful of channels
• How automated post-route verification can relieve the “”expert bottlenecks”
• What it takes to scale post-layout verification to the system level.

Today, for high reliability products, there are more challenges than ever before with tin whiskers and gold embrittlement risks. In 2006 the Restriction of Hazardous Substances (RoHS) Directive took effect in the European Union which aimed to remove materials that pose a risk to the environment and human safety. Since the RoHS Directive took effect, every year more components lead plating systems have changed to either a pure tin or gold finish, resulting in tin whisker or gold embrittlement risk. Today, more than 80 percent of the components available have leads plated with RoHS compliant materials. As a result, high-reliability systems are at risk for failure. In this presentation we will discuss risk impact, critical factors driving these risks, algorithms used to assess risk, and mitigations required to reduce the risk. Also discussed will be strategies suppliers and designers should use in their design process to mitigate risks both at the circuit card assembly level and component level. These strategies incorporate a wealth of industry tested mitigation practices accumulated over time that have been proven effective.

Venturing into the world of flexible circuit design might seem intimidating if you have only designed rigid boards in the past. While flex design does have important differences to be aware of, many of the basic principles are the same. As a designer, it is important to understand how they are different and where the key differences fall in the design process. The goal of this presentation is to provide guidance on what to watch out for in each step of the design process when designing a flex board for the first time.

Key topics to be covered:

• Different types of flex boards: flex, rigid-flex, flex with stiffener
• Importance of early flex fabrication house involvement: stackup, rules, cost
• Stackup considerations: material choices, layer count flexibility
• Mechanical considerations: bend lines and radius, stiffener regions
• Design considerations: footprint modifications, placement guidelines, routing suggestions
• Additional design rules: keepouts around transitions, controlled impedance
• Output files: fabrication drawing details, folded step models

What you will learn:

• The most important differences between rigid and flex design
• Critical questions to ask early in the process
• The importance of collaboration among electrical, mechanical, design and manufacturing early in the process to come up with cost-effective and creative solutions.

Designing PCB power supplies successfully has never been more difficult. Modern ICs have an extremely demanding appetite for high-frequency energy that can be difficult for designers to satisfy with their power delivery system designs. Many common elements can block the energy delivery these ICs require. If this high-frequency energy is not properly delivered, the IC will malfunction in unusual or intermittent ways and/or cause EMI test failures.

Key points covered:

• Power delivery system big picture
• Power delivery system design introduction
• Characteristics of a good PDS
• Conflicting demands placed on the PDS design process
• Steps in designing a power subsystem
• Sources of current demand from the PDS
• Components in the PDS
• Bypass capacitors and inductors
• Ferrite beads
• Inductance of connecting vias
• Capacitor mounting
• Capacitor placement
• Remote sense connections
• Plane capacitance
• Signal plane fills
• Modeling the PDS
• Testing the PDS

What you will learn:

This course focuses on the practical knowledge and design techniques designers need to make a power delivery system support modern IC die power demands. Some types of power system components can have extremely undesirable power system side effects if incorrect component types are selected. Strategies are laid out for designing power delivery systems that yield reliable system designs.

How does one reach the maximum capacity interactions between processor and memory using the new DELL/JEDEC CAMM connector? The demand for speed is here and now from media, CAD, 3-D design, scientific research and data analysis, AI, and machine learning.

This presentation aims to explore through the eyes of the designer the key design challenges when routing DDR5 and from processor and memory placement considerations to maximum speed and performances.

• What is the CAMM2 connector?
• DDR5 vs previous DDR
• SODIMM vs CAMM2
• DDR5 vs LPDDR5
• DRAM layout differences
• Constraint differences
• Placement and pattern of DRAMs
• To mirror or not!
• Sharing command addresses
• Length matching
• Signal Impedance
• Signal integrity
• Power plane capacitors

For a new designer, and even for an experienced designer, component placement can be a daunting task. Where do we start? How do we decide what to prioritize? Are we wasting valuable time by focusing on the wrong things at the wrong time? And, most importantly, what can we do as designers to help solve placement challenges when they arise?

In this presentation, we will work through the placement of a sample design, focusing on the decision-making process. We’ll aim to provide a roadmap any new designer can use to approach component placement on any design. We’ll see firsthand the effects of our decisions and what happens when there are conflicting needs.

What we will cover:

• Preparing a board for component placement
• Deciding which circuits to prioritize first and why
• Planning a “board flow”
• Best design practices
• Circuits with specific placement requirements
• Techniques to help deal with component placement in small spaces
• Fine-tuning circuit placement to comply with board geometries/available space

This session is intended for board designers to understand the “things” RF engineers request during PCB layout. Experienced RF engineers will likely not learn anything new from this course, as the material is mainly geared to board designers.

Due to sensitivity in analog circuits, the keys to full functionality (whether you are designing very high frequency analog PCBs, mixing RF with digital or mixing low frequency analog with digital) are signal integrity and noise control in the design of the printed circuit board. The crux of a great design is contained in the board layout.

This course will discuss and define:

• Microstrip, stripline and CPWG = advantages and disadvantages
• Reflections/return loss/VSWR in lumped vs. distributed lines
• 1/4 wavelength couplers and filters designed into PCB copper
• Basic RF and analog PCB layout techniques and strategies
• Mismatched loads, signal splitters and tuning transmission lines
• RF vs. digital power distribution basics
• PCB stackups for mixed RF and digital circuits

The stackup of a printed circuit board is one of the most important parts of the design layout itself. It affects the way the signals flow on the board itself, and so can affect many other aspects of the functioning board including impedance control, return current, length matching, and the amount of crosstalk, common mode and displacement currents there are, and more. Other important issues are the number of layers needed to account for signals and planes, the dielectric thicknesses used on each layer for balance and to prevent warping, and the way the board is manufactured overall.

In today’s higher speed designs, the electronics mentioned are critical, so we will discuss what is needed for those considerations, plus determining layer count, choosing routing layers, current flow from layer to layer, layer paired routing, building a board stack, and some manufacturing considerations. It is vital to do this step well and to work in conjunction with the fabricator to ensure the needs of both groups are met.

Efficient PCB component placement is a cornerstone in electronic design, influencing both functionality and manufacturability. Improper component placement may result in a multitude of problems impacting the PCB’s functionality, durability, manufacturability,and serviceability.

By strategically placing components, designers can minimize signal crosstalk, mixed signal interference, improve thermal management and mitigate EMC/EMI issues.
This session explores the significance of adept component placement techniques in PCB layout. Proper component placement enhances signal and power integrity, reduces interference, and facilitates ease of assembly, all of which are critical factors in achieving reliable electronic devices.

Fan out and routing of today’s BGAs can be quite challenging! With the overall size of the parts increasing and the pitch between pins decreasing, it can be extremely difficult to get all the signals (and powers) into or out of the part at all, and especially without using many, many layers of the PCB.

If the designer uses some creativity to set up patterns of signals and vias, the fanout can be completed for all the signals, while using the layers of the board efficiently. The signals will also need to maintain a good return path, signal integrity and EMI control, which makes things even more complicated. We will discuss the thought and preparation to address these issues. Additionally, we go over manufacturing concerns unique to the newer BGAs because of their small pad sizes, the trace widths needed, and the small capacitors used.

In this 3.5-hour presentation, we will discuss all those things and more including choosing effective BGAs, the placement of caps, power and stackup information, and grid systems for through hole and microvia fanout.

“In the world of printed circuit board design, ADC (analog to digital converters) and DACs (digital to analog converters) play an important role in the modern world. This seminar is concentric around techniques used in printed circuit designs. Topic discussed and detailed will include noise reduction techniques for power distribution, input/output protection for transients as well as how to protect against ESD events.
This presentation aims to explore the key considerations, challenges, and techniques involved in designing efficient via structures to achieve enhanced performance and reliability.

Key points covered include:

• Noise reduction for ADC/DACs
• Signal integrity and design considerations
• Power distribution
• Design guidelines and optimization techniques
• Case studies and best practices

What you will learn:

• Design for noise reduction
• Specific techniques to use and ones to avoid
• Analog vs. digital gorund: why or why not?

This presentation will cover typical boards for speeds under 500MHz (typically FR-4, etc.)”

This course will walk through the entire multilayer PCB fabrication process, making stops to explain how PCB design requirements affect the numerous fabrication steps and if/how the finished product can meet the intended quality and reliability requirements. A detailed explanation will be given for each of the process steps and how that step affects quality and reliability.

Key topics to cover:

• Design requirements, with an explanation of the dos and don’ts of how they affect fabrication and impact yields
• Process controls adopted by the fabricator to ensure maximum yields and quality are maintained during each step of fabrication
• Pros and cons of variables available to the designer:
  • Solder mask
  • Surface finish
  • Materials selection
  • Copper weights
  • Feature size, etc.

The course also looks at fabrication drawing specifications and how they can affect yield, cost, quality and reliability.”

Engineering and design teams are increasingly driven to integrate AI technologies that:

• Use LLMs, neural networks, and reinforcement learning
• Accelerate design workflows (schematic, layout) and reduce time-to-market.
• Reduce cost across the design cycle
• Reduce risk and minimize errors in complex design tasks.
• Keep their teams and business ahead of the competition.

The purpose of this master class is to equip designers and engineers with the knowledge to accelerate their workflows using AI tools. This no-nonsense course focuses on leveraging AI tools in the hardware design workflow. We will explore the time and resources involved in a typical design process and then dive into each of these processes to demonstrate how the presented tools can accelerate workflows across all ecosystems, such as automotive, defense and medical. For the sake of familiarity, this class will build on popular open-source projects. While specific vendors will be mentioned, our focus will be on the frameworks for interacting with these tools.
This course will equip participants with the knowledge to alleviate fears that these tools will replace us, and instead show how they can become valuable allies. Once equipped with this knowledge, participants can approach their hardware design cycles with the enhanced capabilities of AI-driven workflows. Additionally, this course presents a pattern of thinking that helps keep pace with technological advancements, preparing you to evaluate the effectiveness of new tools as they emerge.

This course is for:

• All levels of electrical engineers
• All levels of PCB designers
• Product development teams

Included in the course we will introduce:

• A no-nonsense approach with practical examples and workflows on how to integrate AI into current design processes for all design ecosystems
• Establishing knowledge and frameworks that will apply to current and future AI tools
• Methods that apply to the entire hardware design cycle – libraries, schematics, layout, and BoMs
• Understanding the real limitations of the tools and what’s to come.

Creating your own designs from scratch demands not only technical skill and dedication but also the ability to approach a project from multiple perspectives. This technical seminar will explore a custom FPGA system on module printed circuit board from the perspectives of project management, hardware design, and FPGA engineering.

Starting by delving into communication loops, the seminar will emphasize the importance of clear project requirements and ongoing refinement through discussions. Real-world deployment use cases will highlight the design inspiration that helped to drive the project criteria.

With a launch point established, the seminar will then showcase schematic creation, focusing on learning tools and implementation strategies for continuous improvement. Included with this will be the initial PCB layout, with a focus on design reuse, which is critical for efficient development, especially considering that multiple hardware designs will be created from this initial template. This section will showcase the transfer between projects, techniques for designing reusable blocks, and the significance of reuse in software/firmware integrated projects.

The seminar will then address the often-underestimated importance of grounding, utilizing examples from the FPGA power distribution and pinouts, and applying them to custom connector pinout design. Examples of BGA routing breakout will be discussed, along with an analysis of the “”bring up”” phase. Additionally, we’ll touch on FPGA basics and implementation within the broader design context.

Finally, the presentation will address multi-part compatibility, emphasizing the standardization of interfaces and integration into carrier boards or other designs. Throughout, we will draw on real-world examples and lessons learned, sharing insights into common mistakes, providing actionable takeaways for PCB designers at all levels, and highlighting the necessity of tracking all items through revision logs. For hands-on reference, completed design samples will be readily available for participants to interact with.

In the dynamic realm of electronics, completing a PCB layout is just the tip of the iceberg. The real challenge lies in seamlessly signing off the design and generating the manufacturing release. The significance of having comprehensive documentation, thorough checklists, and strategic review meetings before any design release cannot be overstated.
In the fast-paced world of technology, where time to market is a decisive factor in product success, hasty design releases can prove to be detrimental. Organizations often face nightmares when crucial elements are overlooked. History provides cautionary tales, such as the downfall of giants like Kodak and RIM (Blackberry phones), underscoring the importance of timely product launches.

In this session we’ll explore the importance of comprehensive documentation, checklists, and thorough review meetings prior to design release.