With continuous technological developments, electronic circuits are not only becoming faster and smaller but also more power-hungry. Consequently, related thermal issues are more prevalent than ever because most modern PCBs consist of numerous high-power components such as high-performance processors, transceivers, Mosfets, and high-power LEDs, leading to excessive heat. Additionally, power conversion circuitry, including DC-DC converters and regulators, contributes significantly to temperature elevation and hotspots. Besides the components, the resistance of the electrical connections, copper traces, and vias contribute to heat, and power losses.

Thermal stress stands out as a primary cause of circuit malfunction, resulting in performance degradation or even system malfunction or failure. To address thermal stresses at the layout level, PCB designers must incorporate effective techniques to reduce heating impacts. This includes careful material selection, strategic component placement, power ground plane construction, thermal vias, and more.

This presentation will explore these effective strategies and tricks that layout engineers can adopt to identify and mitigate major hotspots, ultimately enhancing the thermal performance of PCBs.

Designing a PCB when you are not involved in the schematic or mechanical development presents unique challenges. Recognizing these knowledge gaps early and addressing them proactively can greatly enhance the efficiency and quality of the final layout. This presentation will provide actionable strategies for designers to navigate the process of PCB layout from input review through generating final outputs.

Key topics to be covered:

• Input review: Pre-existing files and library requirements
• Establishing design constraints: Mechanical input and electrical specifications
• Manufacturing considerations: Capabilities, DfM, and documentation
• Balancing tradeoffs: Time, cost and performance considerations.

What you will learn:

• Key conversations to have upfront to streamline your design process
• Best practices for aligning with your team early and consistently
• How to position yourself as a key resource for the design team.

This presentation delves into the critical role of vias in ensuring signal integrity by providing optimal return paths in printed circuit boards (PCBs). We’ll explore why a well-defined return path is crucial for containing electromagnetic fields and minimizing noise. This knowledge will be built upon the foundation that planes are the optimal solution for field containment, but are unable to enable return path in the z-axis.

Attendees will gain a practical understanding of via behavior through simulations, starting with common design pitfalls and progressing towards optimized solutions. We’ll analyze real-world scenarios and demonstrate how strategic via placement and design choices can significantly improve signal integrity.

Finally, we’ll examine advanced techniques, including the concept of a “via-in-via” structure for achieving coaxial-like return paths. The session will conclude with guidance on selecting components, such as BGAs, with optimized ground return paths to further enhance PCB performance, ensuring design success.

Key topics to cover:

• The importance of return paths for signal integrity and EMI mitigation
• Learn how to effectively utilize vias to optimize return paths
• Discover advanced via design techniques for high-performance PCBs
• Gain practical knowledge for selecting components with superior return path characteristics

In an era where electronic systems transcend traditional flat-plane constraints, three-dimensional molded interconnect devices (3D-MIDs) are revolutionizing how we approach circuit design. This 2-hour session introduces the fundamentals of MID technology–encompassing materials, manufacturing techniques, and design strategies–while highlighting its transformative potential for mechanical-electrical integration.

Key topics to cover:

• Fundamentals of MID technology, highlighting the advantages of 3-D molded interconnect devices over traditional planar PCBs and flex circuits
• Comparing two-shot molding with laser direct structuring (LDS) to illustrate different manufacturing techniques and their impact on design fidelity
• Providing a holistic view of the 3D-MID ecosystem, including materials selection, design platforms, data formats, and effective collaboration with MID fabricators

Further, the seminar will delve into the diverse landscape of materials, design workflows, and manufacturing strategies:

• Examining a range of LDS-grade materials and their suitability for various mechanical, thermal, RF and biocompatible requirements
• Demonstrating practical design workflows across various ECAD/MCAD tools, and exploring component placement, 3-D part integration, and advanced routing techniques tailored to 3-D surfaces
• Addressing critical design guidelines, including wall thickness, surface quality, mold tool considerations, through-holes, trace geometries, and metallization strategies that enable reliable, functional 3-D circuits
• Exploring the end-to-end manufacturing process – from injection molding and laser activation to metallization and component assembly – highlighting both barrel and rack plating methods as well as prototyping options like 3-D printing and soft tooling.

Participants will leave with a depth of understanding encompassing:

• Practical insights into identifying when and why 3D-MID technology adds value, including applications in sensors, antennas, wearable devices, and organic-shaped electronics
• Strategies for reducing design complexity, optimizing form factors, and improving functionality through fully integrated, three-dimensional layouts
• A clear roadmap for effectively navigating the design-to-production process, leveraging design platforms, manufacturing partnerships, and prototyping methods to achieve robust, innovative 3D circuit solutions.

As thermal density in high power electronics continues to increase, the ability to manage heat precisely at the component level has become critical. This study presents direct temperature measurements of Mosfet heat sources across multiple configurations of PCB substrates and thermal enhancement components. Specifically, it evaluates the thermal performance of a high conductivity dielectric from TCLAD, compared to traditional FR-4, using a quadrant-based test board populated with SOT223 power transistors and surface mount thermal bridge (SMTB) components.

The test vehicle was a six-layer PCB, engineered with four identical quadrants, each containing four ZETEX FZ493 SOT223 transistors as heat generating components. This symmetrical layout permitted direct, side-by-side comparisons of different thermal configurations under identical electrical loads and copper geometries. Quadrant 1 featured no SMTBs (serving as the baseline), quadrant 2 included a small SMTB (SMTB2114P30E), quadrant 3 a medium SMTB (SMTB3123A30A), and quadrant 4 a large SMTB (SMTB2920P30E). Both FR-4 and the novel versions of the test board were fabricated and assembled identically to isolate the thermal impact of the dielectric and thermal bridge materials.

Thermal imaging revealed that the novel substrate significantly outperformed FR-4, reducing maximum component temperatures by up to 48°F (26.6°C) in quadrant 1, where no SMTBs were used. When paired with the largest SMTBs in quadrant 4, the novel board achieved a total temperature reduction of 29°C compared to the FR-4 board in quadrant 1. This result clearly demonstrates the combined thermal benefits of using a high-conductivity dielectric material alongside strategically placed heat-spreading components.

Today, we are witnessing a transformation driven by artificial intelligence (AI), which is dramatically enhancing productivity across various industries. In particular, some organizations are leveraging AI to streamline the exchange of design-to-manufacturing data for printed circuit boards. When AI systems are provided with precise and well-structured data, they can optimize workflows, anticipate potential issues, and foster ongoing improvements.

Prevalent use of unstructured formats – such as Gerber packages – poses significant obstacles, however. Inconsistent or incomplete information in these formats can result in errors and unreliable outputs from AI systems. Key challenges include:

• Multiple files: Discrepancies between drawing dimensions and Gerber data force AI to determine which information is accurate, often leading to incorrect assumptions.
• Netlist problems: IPC-D-356 files may omit intentional shorts or opens, causing test failures and necessitating additional manual verification.
• Drill table issues: Variations in hole counts require clarification, which can delay the manufacturing process.

Adopting IPC-2581 – a robust, open, and intelligent standard for bidirectional data exchange – offers a solution. IPC-2581 provides consistent, AI-ready data that minimizes errors, lowers costs, saves time, and enables true automation and seamless collaboration in the PCB manufacturing workflow.

In summary, while Gerber data often lead to unreliable outcomes when processed by AI, IPC-2581 delivers structured and dependable information essential for effective AI-driven automation. Relying on intelligent data standards like IPC-2581 is key to unlocking the full potential of AI in PCB manufacturing.

In preparation for this presentation, we talked to many of the largest PCB manufacturers in the US and abroad. We then developed a list of the most common errors found on incoming designs. We look at each of the errors and discuss ways to find them before the designs are sent out for manufacturing. The methods we will look at include netlist comparison, design for manufacturing and design rule analysis. We also talk about proper documentation needed for PCB manufacturing. We encourage attendee participation and ask folks to bring their challenges for discussion. After this seminar, the PCB designer will take back some knowledge to better assist them in using their existing tools in the market to produce better and more accurate designs.

This presentation addresses design for manufacturing (DfM) principles tailored for ultra-high-density interconnects (UHDI) in advanced PCB technology. UHDI, characterized by 25-micron feature sizes and below, enables higher wiring densities essential for modern applications such as smartphones, IoT devices, automotive systems, 5G infrastructure and medical electronics. The document emphasizes the critical role of DfM in ensuring manufacturability, cost efficiency, and high yield amidst the growing miniaturization and complexity of UHDI designs.

Key topics include emerging trends like AI-driven design optimization, challenges in UHDI design and manufacturing, and the principles of DFM tailored for UHDI. The discussion highlights the importance of collaboration between designers and manufacturers to address complexities such as high wiring density, material compatibility, and thermal management. The adoption of design guidelines, including trace width optimization, EMI compliance, and thermal relief, underscores the need for early integration of DFM principles to achieve scalable and robust designs.

In conclusion, this abstract addresses DFM for UHDI. It advocates standardization, interdisciplinary collaboration and technological innovation to advance UHDI development and manufacturing processes, paving the way for future technologies.

Key topics to cover:

• DfM principles tailored for UHDI and why industry standardization for UHDI is needed
• Emerging trends like AI-driven design optimization and challenges in UHDI design from both design and manufacturing perspectives
• The importance of collaboration between designers and manufacturers to address complexities such as high wiring density, material compatibility and thermal management.

Printed circuit board (PCB) design plays a decisive role in product performance, reliability, and manufacturability. Yet, over 30% of PCB designs require modification before fabrication due to overlooked details, CAD system defaults, or a lack of alignment with industry standards.

This presentation distills years of manufacturing experience into two practical tools. These design tips highlight the 13 most common design mistakes and their costly implications, coupled with a structured step-by-step framework for validating designs before release. Together, these resources equip engineers, designers, and production teams to reduce errors, improve first-pass yield, and ensure high-reliability PCBs that meet IPC standards.

Attendees will gain actionable strategies for avoiding pitfalls such as annular ring violations, copper-to-edge spacing issues, solder mask misalignments, and silkscreen conflicts, while also learning how to systematically apply design checks across component packaging, routing, timing, power integrity, and Gerber review. The session empowers professionals to get it right the from the start, saving cost, time and ensuring product quality in today’s fast-paced electronics market.

Who should attend: PCB Designer/Design Engineer, Hardware Engineer, SI Engineer, Test Engineer, Fabricator Engineer/Operator, Assembly Engineer/Operator

This presentation is part of a multiyear ongoing conversation at PCB East and West to give insight into growing trends and threats in the PCB design (and by extension, fab and assembly) industry. I will touch very lightly on many subjects to try to raise awareness for the community so we are not left behind in our careers as the industry continues to evolve. I am basing the information on conversations with industry leaders and experts. What are they seeing? What are we missing? What do they think we need to be looking at to be prepared for the next 2-5 years? I will be collecting this information and weaving it into the talk.

Key points that I am following and presenting (though this list continues to change):

• The current state of AI in PCB design
• Interposer boards (between PCBs and semiconductors)
• High-speed/high-current update – Where are we now, where are we heading
• Optics
• Where are designers coming from

This is intended as an overview to provide exposure to coming trends. It will not be a deep technical dive into any of these subjects. The aim is to provide enough information for users to prepare on where the industry might be headed. This may help inform career directions, opportunities and choices to consider in the coming years.

Why does the topic of library management often evoke groans and frustration among PCB designers? Libraries – comprising schematic symbols, PCB footprints, and 3D models—are essential to the design process, yet managing them is frequently seen as tedious and time-consuming.

This presentation takes a candid look at the common pain points of library management, from inconsistent naming conventions and outdated components to the challenges of maintaining accuracy and version control. We’ll also explore strategies to make library management more efficient and less painful, including best practices for standardization, leveraging automated tools, and integrating third-party libraries.

Whether you love them or hate them, libraries are a critical part of PCB design, and this session will offer practical advice to help you tame the chaos and build a library system that works for you.

Many engineers are now required to design their own PCBs, but they have not had the benefit of learning the particular needs of the electronics, signals, placement, routing and stackups in those boards. This presentation will feature an overview of the processes of board design from an engineering perspective.

Topics that will be covered:

• How electronics and physics are involved in signaling
• Why controlling rise time, field energy, transmission lines and impedance are critical to the behavior of signals on the board
• Parts selection criteria
• Placement planning (flow, order, and setting up the potential routing and bus channels that are to come)
• Power input (capacitors, their connections, interplane capacitance and the power delivery system) Planes and stackups and their needs and contributions to board function
• Overall routing possibilities; fanout ideas and designs
• What is needed for routing signals and busses

We will close out the technical presentation with specific information for designing high-frequency energy including crosstalk, antennas and EMI. If there is enough time, we will discuss a few things that help make a board more manufacturable, thus making it less expensive.

Differential signaling has become a cornerstone of modern high speed digital design, enabling reliable data transmission across interfaces such as USB, PCI Express, HDMI, and multi gigabit Ethernet. Yet despite its widespread use, misconceptions persist about how differential pairs behave on printed circuit boards. Many designers assume that PCB based differential pairs operate like twisted pair cables, when in reality the electromagnetic environment, physical geometry, and return path behavior on a PCB introduce unique challenges that must be understood to ensure signal integrity.
This session provides a comprehensive exploration of differential pair routing from both a theoretical and practical perspective. We begin by examining the electrical characteristics of differential lines, including impedance, coupling, and common mode behavior. The discussion then moves into key layout considerations such as trace spacing, length matching tolerances, crosstalk mechanisms, and the impact of fiber weave skew on timing alignment. Special attention is given to via transitions, layer changes, and stack up design, highlighting how each influences impedance balance and signal quality.
Participants will also learn best practice termination strategies and how to evaluate differential performance using simulation tools and measurement techniques. Real world examples illustrate common pitfalls – such as inconsistent spacing, plane crossings, and excessive via usage – and demonstrate practical methods to avoid them.
By the end of this two hour course, attendees will gain a clear, actionable framework for routing differential pairs that meet the electrical, mechanical, and manufacturability requirements of today’s high speed systems. Whether you are refining existing design skills or tackling differential routing for the first time, this session delivers the insight needed to build robust, high performance PCB interconnects.

This two-hour course will discuss and define:

• Characteristics of differential pair lines
• Impact of line-to-line spacing on signal integrity
• Line length (timing) matching – how tightly?
• Impact of crosstalk on diff pair behavior
• Issues that cause timing skew, including fiber weave
• Best diff pair line termination schemes
• Changing layers with differential signals.

Designers often learn about electromagnetic compatibility (EMC) in the context of failing an EMC test and spending hours, days, or weeks troubleshooting in the lab. This course aims to teach fundamentals and design principles that will enable engineers to create hardware with a better chance of passing EMC testing the first time. These fundamentals are applicable to electrical and electronics design in any industry.

Key topics to cover:

• What is EMC?
• Where high frequency noise is generated even in DC/low frequency systems
• Why structures can act like antennas
• Non-ideal performance of components
• Parasitic capacitance.

What you will learn:

• How to identify the highest risk areas of design that cause most EMC test failures
• Mitigations for those high-risk areas.

In all high-speed/high-frequency circuits, signal integrity is dependent on several variables, all of which accumulate to impact the noise budget of the circuit. With very high-speed circuits, an even larger number of issues come into play, and all the effects are more extreme. Problems can be driven by design deficiencies, some by the physical structure and design of the ICs, and still more are driven by the PCB’s copper style and base material parameters.

Key topics to cover:

• Signal noise budgets and attenuation basics
• Signal jitter and inter-symbol interference
• Basics of transmission line discontinuities
• Cause and effect of ground and VCC bounce
• Cause of skin effect and loss tangent issues
• Impact of pre-emphasis and equalization
• Via stubs and cost-effective solutions.

Anyone assigned the responsibility of laying out a PCB in a professional setting has faced the challenge of managing expectations for stakeholders throughout the process. The biggest point of contention and area of struggle for designers (novice and experts alike) is often answering the question of how long they think it will take to lay out the circuit board. It’s not unheard of for the question to incite anxiety, frustration and anger among even the most experienced designers.

To make matters worse, widespread distribution of misinformation has become a driving source of misunderstandings, myths and misconceptions about this process and has set the stage for preemptive unrealistic expectations from relevant stakeholders who may be more distanced from the work. The list of stakeholders includes, but is not limited to, project managers, mechanical engineers, electrical engineers, test engineers, team leads, supervisors, division leadership, customers, supply chain managers, manufacturer/assembly vendors, end-users, sales and marketing.

This presentation will help build a reliable framework for those laying out the PCB to assess the work required to complete the job so they can provide a rough estimate to stakeholders how long the job will take. The focus is on factors to consider and questions to ask as one puts together an estimate. It also provides insights to relevant stakeholders who are interested in better understanding the process and/or discerning common misconceptions about what actually impacts layout time.

This body of work was a curation of the presenter’s professional experience, anecdotes from experienced coworkers, and insight from industry experts who will be recognized (with their consent, of course) for their contribution. In the spirit of shared learning and building the collective knowledge base, time will be allotted for participants to share experiences.

Power distribution in PCBs is the foundation around which all things work in the circuit. If this structure is not designed correctly the entire circuit is at risk from noise and signal integrity issues, to say nothing of the severely increased possibility of EMI. Low impedance in the power distribution network across the harmonic frequency range of a digital circuit is critical. There are many subtle PCB layout techniques that have major impact on power bus impedance.

• Impedance of vias, planes and mounted inductance of capacitors
• Energy delivery to IC cores and impact of IC pin out on bus impedance
• Placement of decoupling in both moderate and high-layer-count PCBs
• Multiple capacitor values and how to resolve anti-resonant peaks
• Effect of ferrites in the power bus, in digital and analog circuits
• Importance of power/ground plane pairs and impact of ultra-thin pairs
• Extreme importance of PCB stackup for best power delivery.

A well-designed PCB stackup can significantly influence the performance and longevity of an electronic product. It affects signal integrity, power distribution, impedance control, thermal performance, and mechanical reliability. Conversely, a poorly chosen stackup can lead to issues such as crosstalk, electromagnetic interference (EMI), excessive heat generation, and reduced durability, resulting in higher production costs and increased time-to-market. By understanding the foundational principles of stackup design, designers can address these challenges early in the design process and ensure successful implementation.

Topics covered:

• Fundamentals of PCB stackup design: Core concepts and definitions for rigid, flex, and rigid-flex boards.
• Material selection: How to choose laminates, prepregs, and adhesives for different applications.
• Impedance control: Techniques for achieving consistent impedance across signal layers.
• Signal integrity: Managing high-speed signals and reducing crosstalk and EMI.
• Thermal considerations: Addressing heat dissipation in complex designs.
• Mechanical reliability: Ensuring durability in flex and rigid-flex boards under dynamic conditions.
• Manufacturability: Guidelines to optimize stackup design for cost-effective fabrication.
• Layer count optimization: Balancing performance needs with cost constraints.
• Real-world examples: Case studies demonstrating effective stackup design strategies.

What you will learn:

• A comprehensive understanding of stackup design principles for rigid, flex, and rigid-flex PCBs.
• How to select materials that meet electrical, thermal, and mechanical requirements.
• Mastering impedance and signal integrity management techniques for high-performance designs.
• Strategies to optimize stackup configurations for manufacturability and cost efficiency.
• How to design for thermal performance and reliability in challenging applications.
• Explore real-world scenarios that highlight the impact of effective stackup design.
• Actionable insights into minimizing crosstalk, EMI, and other performance issues.
• Skills to collaborate effectively with fabricators and ensure design intent is achieved.

This presentation is ideal for PCB designers, engineers, and anyone involved in the development of electronic systems who seeks to enhance their expertise in stackup design.

Designing a PCB when you are not involved in the schematic or mechanical development presents unique challenges. Recognizing these knowledge gaps early and addressing them proactively can greatly enhance the efficiency and quality of the final layout. This presentation will provide actionable strategies for designers to navigate the process of PCB layout from input review through generating final outputs.

Key topics to be covered:

• Input review: Pre-existing files and library requirements
• Establishing design constraints: Mechanical input and electrical specifications
• Manufacturing considerations: Capabilities, DfM, and documentation
• Balancing tradeoffs: Time, cost and performance considerations.

What you will learn:

• Key conversations to have upfront to streamline your design process
• Best practices for aligning with your team early and consistently
• How to position yourself as a key resource for the design team.

Circuit board assemblies today include more high-speed circuitry than ever before, making it difficult to meet all requirements, perform robustly in real-world conditions, and pass agency tests such as FCC. Live demonstrations included! Audience discussion is encouraged, and there will be time for questions and answers.

Key points to be covered:

• How this impacts agency testing (and how to pass the tests!)
• Discuss common problems and how to avoid them
• Discuss some recommended PCB stackups

What you will learn:

• Why every design needs to consider high-frequency layout
• Why EMI (electromagnetic interference) and SI (signal integrity) matter
• Comparison of circuit theory and wave theory
• The difference between ground and return.

Engineering and design teams are increasingly driven to integrate AI technologies that:

• Use LLMs, neural networks and reinforcement learning
• Accelerate design workflows (schematic, layout) and reduce time-to-market
• Reduce cost across the design cycle
• Reduce risk and minimize errors in complex design tasks
• Keep their teams and business ahead of the competition.

The purpose of this master class is to equip designers and engineers with the knowledge to accelerate their workflows using AI tools. This no-nonsense course focuses on leveraging AI tools in the hardware design workflow. We will explore the time and resources involved in a typical design process and then dive into each of these processes to demonstrate how the presented tools can accelerate workflows across all ecosystems, such as automotive, defense and medical. For the sake of familiarity, this class will build on popular open-source projects. While we will mention specific vendors, our focus will be on the frameworks for interacting with these tools.

This course will alleviate fears that these tools will replace us and instead show how they can become valuable allies. Once equipped with this knowledge, participants can approach their hardware design cycles with the enhanced capabilities of AI-driven workflows. Additionally, it will help you keep pace with technological advancements, preparing you to evaluate the effectiveness of new tools as they emerge.

This course is for:

• All levels of electrical engineers
• All levels of PCB designers
• Product development teams

What you will learn:

• A no-nonsense approach with practical examples and workflows on how to integrate AI into current design processes for all design ecosystems
• How to establish knowledge and frameworks that will apply to current and future AI tools
• Methods that apply to the entire hardware design cycle: libraries, schematics, layout and BoMs
• The real limitations of the tools and what’s to come.

Creating your own designs from scratch demands not only technical skill and dedication but also the ability to approach a project from multiple perspectives. This technical seminar will explore a custom FPGA system on module printed circuit board from the perspectives of project management, hardware design, and FPGA engineering.
Starting by delving into communication loops, the seminar will emphasize the importance of clear project requirements and ongoing refinement through discussions. Real-world deployment use cases will highlight the design inspiration that helped to drive the project criteria.
With a launch point established, the seminar will then showcase schematic creation, focusing on learning tools and implementation strategies for continuous improvement. Included with this will be the initial PCB layout, with a focus on design reuse, which is critical for efficient development, especially considering that multiple hardware designs will be created from this initial template. This section will showcase the transfer between projects, techniques for designing reusable blocks, and the significance of reuse in software/firmware integrated projects.

The seminar will then address the often-underestimated importance of grounding, utilizing examples from the FPGA power distribution and pinouts, and applying them to custom connector pinout design. Examples of BGA routing breakout will be discussed, along with an analysis of the “”bring up”” phase. Additionally, we’ll touch on FPGA basics and implementation within the broader design context.
Finally, the presentation will address multi-part compatibility, emphasizing the standardization of interfaces and integration into carrier boards or other designs. Throughout, we will draw on real-world examples and lessons learned, sharing insights into common mistakes, providing actionable takeaways for PCB designers at all levels, and highlighting the necessity of tracking all items through revision logs. For hands-on reference, completed design samples will be readily available for participants to interact with.